#!/usr/bin/python import sys,pxa try: import bdi except ImportError: pass regs = { "PMCR": ["3-21", "Power Manager Control Register", pxa.PMCR, [ ["IDAE", "PM imprecise data abort abort signal", "d", 0, 0 ],], ], "PCFR": ["3-22", "Power Manager General Configuration Register", pxa.PCFR, [ ["OPDE", "PM stop 3.6864 MHz oscillator during sleep", "ldena", 0, 0 ], ["FP", "PM float PCMCIA signals during sleep", "ldena", 1, 1 ], ["FS", "PM float static chip select signals during sleep", "ldena", 2, 2 ],], ], "PWER": ["3-23", "Power Manager Wake-Up Enable Register", pxa.PWER, [ ["WE0", "PM wake up due to GPIO 0 edge detect", "ldena", 0, 0 ], ["WE1", "PM wake up due to GPIO 1 edge detect", "ldena", 1, 1 ], ["WE2", "PM wake up due to GPIO 2 edge detect", "ldena", 2, 2 ], ["WE3", "PM wake up due to GPIO 3 edge detect", "ldena", 3, 3 ], ["WE4", "PM wake up due to GPIO 4 edge detect", "ldena", 4, 4 ], ["WE5", "PM wake up due to GPIO 5 edge detect", "ldena", 5, 5 ], ["WE6", "PM wake up due to GPIO 6 edge detect", "ldena", 6, 6 ], ["WE7", "PM wake up due to GPIO 7 edge detect", "ldena", 7, 7 ], ["WE8", "PM wake up due to GPIO 8 edge detect", "ldena", 8, 8 ], ["WE9", "PM wake up due to GPIO 9 edge detect", "ldena", 9, 9 ], ["WE10", "PM wake up due to GPIO10 edge detect", "ldena", 10, 10 ], ["WE11", "PM wake up due to GPIO11 edge detect", "ldena", 11, 11 ], ["WE12", "PM wake up due to GPIO12 edge detect", "ldena", 12, 12 ], ["WE13", "PM wake up due to GPIO13 edge detect", "ldena", 13, 13 ], ["WE14", "PM wake up due to GPIO14 edge detect", "ldena", 14, 14 ], ["WE15", "PM wake up due to GPIO15 edge detect", "ldena", 15, 15 ], ["WERTC", "PM wake up due to RTC alarm", "ldena", 31, 31 ],], ], "PRER": ["3-24", "Power Manager Rising Edge Detect Enable Register", pxa.PRER, [ ["RE0", "PM wake up due to GPIO 0 rising edge detect", "ldena", 0, 0 ], ["RE1", "PM wake up due to GPIO 1 rising edge detect", "ldena", 1, 1 ], ["RE2", "PM wake up due to GPIO 2 rising edge detect", "ldena", 2, 2 ], ["RE3", "PM wake up due to GPIO 3 rising edge detect", "ldena", 3, 3 ], ["RE4", "PM wake up due to GPIO 4 rising edge detect", "ldena", 4, 4 ], ["RE5", "PM wake up due to GPIO 5 rising edge detect", "ldena", 5, 5 ], ["RE6", "PM wake up due to GPIO 6 rising edge detect", "ldena", 6, 6 ], ["RE7", "PM wake up due to GPIO 7 rising edge detect", "ldena", 7, 7 ], ["RE8", "PM wake up due to GPIO 8 rising edge detect", "ldena", 8, 8 ], ["RE9", "PM wake up due to GPIO 9 rising edge detect", "ldena", 9, 9 ], ["RE10", "PM wake up due to GPIO10 rising edge detect", "ldena", 10, 10 ], ["RE11", "PM wake up due to GPIO11 rising edge detect", "ldena", 11, 11 ], ["RE12", "PM wake up due to GPIO12 rising edge detect", "ldena", 12, 12 ], ["RE13", "PM wake up due to GPIO13 rising edge detect", "ldena", 13, 13 ], ["RE14", "PM wake up due to GPIO14 rising edge detect", "ldena", 14, 14 ], ["RE15", "PM wake up due to GPIO15 rising edge detect", "ldena", 15, 15 ],], ], "PFER": ["3-25", "Power Manager Falling Detect Enable Register", pxa.PFER, [ ["FE0", "PM wake up due to GPIO 0 falling edge detect", "ldena", 0, 0 ], ["FE1", "PM wake up due to GPIO 1 falling edge detect", "ldena", 1, 1 ], ["FE2", "PM wake up due to GPIO 2 falling edge detect", "ldena", 2, 2 ], ["FE3", "PM wake up due to GPIO 3 falling edge detect", "ldena", 3, 3 ], ["FE4", "PM wake up due to GPIO 4 falling edge detect", "ldena", 4, 4 ], ["FE5", "PM wake up due to GPIO 5 falling edge detect", "ldena", 5, 5 ], ["FE6", "PM wake up due to GPIO 6 falling edge detect", "ldena", 6, 6 ], ["FE7", "PM wake up due to GPIO 7 falling edge detect", "ldena", 7, 7 ], ["FE8", "PM wake up due to GPIO 8 falling edge detect", "ldena", 8, 8 ], ["FE9", "PM wake up due to GPIO 9 falling edge detect", "ldena", 9, 9 ], ["FE10", "PM wake up due to GPIO10 falling edge detect", "ldena", 10, 10 ], ["FE11", "PM wake up due to GPIO11 falling edge detect", "ldena", 11, 11 ], ["FE12", "PM wake up due to GPIO12 falling edge detect", "ldena", 12, 12 ], ["FE13", "PM wake up due to GPIO13 falling edge detect", "ldena", 13, 13 ], ["FE14", "PM wake up due to GPIO14 falling edge detect", "ldena", 14, 14 ], ["FE15", "PM wake up due to GPIO15 falling edge detect", "ldena", 15, 15 ],], ], "PEDR": ["3-26", "Power Manager Edge Detect Status Register", pxa.PEDR, [ ["ED0", "PM wake up due to edge on GPIO 0", "lddet", 0, 0 ], ["ED1", "PM wake up due to edge on GPIO 1", "lddet", 1, 1 ], ["ED2", "PM wake up due to edge on GPIO 2", "lddet", 2, 2 ], ["ED3", "PM wake up due to edge on GPIO 3", "lddet", 3, 3 ], ["ED4", "PM wake up due to edge on GPIO 4", "lddet", 4, 4 ], ["ED5", "PM wake up due to edge on GPIO 5", "lddet", 5, 5 ], ["ED6", "PM wake up due to edge on GPIO 6", "lddet", 6, 6 ], ["ED7", "PM wake up due to edge on GPIO 7", "lddet", 7, 7 ], ["ED8", "PM wake up due to edge on GPIO 8", "lddet", 8, 8 ], ["ED9", "PM wake up due to edge on GPIO 9", "lddet", 9, 9 ], ["ED10", "PM wake up due to edge on GPIO10", "lddet", 10, 10 ], ["ED11", "PM wake up due to edge on GPIO11", "lddet", 11, 11 ], ["ED12", "PM wake up due to edge on GPIO12", "lddet", 12, 12 ], ["ED13", "PM wake up due to edge on GPIO13", "lddet", 13, 13 ], ["ED14", "PM wake up due to edge on GPIO14", "lddet", 14, 14 ], ["ED15", "PM wake up due to edge on GPIO15", "lddet", 15, 15 ],], ], "PSSR": ["3-27", "Power Manager Sleep Status Register", pxa.PSSR, [ ["SSS", "PM chip was in sleep by setting sleep mode bit", "d", 0, 0 ], ["BFS", "PM nBATT_FAULT has been asserted", "d", 1, 1 ], ["VFS", "PM nVDD_FAULT was asserted while in Run or Idle", "d", 2, 2 ], ["PH", "PM GPIO pins are held in their sleep state", "d", 4, 4 ], ["RDH", "PM receivers of all input GPIO are disabled", "d", 5, 5 ],], ], "PSPR": ["3-28", "Power Manager Scratch Pad Register", pxa.PSPR, [], ], "PGSR0": ["3-29", "Power Manager GPIO Sleep State Register 0", pxa.PGSR0, [ ["S0", "PM GPIO pin 0 is during sleep", "d", 0, 0 ], ["S1", "PM GPIO pin 1 is during sleep", "d", 1, 1 ], ["S2", "PM GPIO pin 2 is during sleep", "d", 2, 2 ], ["S3", "PM GPIO pin 3 during sleep", "d", 3, 3 ], ["S4", "PM GPIO pin 4 during sleep", "d", 4, 4 ], ["S5", "PM GPIO pin 5 during sleep", "d", 5, 5 ], ["S6", "PM GPIO pin 6 during sleep", "d", 6, 6 ], ["S7", "PM GPIO pin 7 during sleep", "d", 7, 7 ], ["S8", "PM GPIO pin 8 during sleep", "d", 8, 8 ], ["S9", "PM GPIO pin 9 during sleep", "d", 9, 9 ], ["S10", "PM GPIO pin 10 during sleep", "d", 10, 10 ], ["S11", "PM GPIO pin 11 during sleep", "d", 11, 11 ], ["S12", "PM GPIO pin 12 during sleep", "d", 12, 12 ], ["S13", "PM GPIO pin 13 during sleep", "d", 13, 13 ], ["S14", "PM GPIO pin 14 during sleep", "d", 14, 14 ], ["S15", "PM GPIO pin 15 during sleep", "d", 15, 15 ], ["S16", "PM GPIO pin 16 during sleep", "d", 16, 16 ], ["S17", "PM GPIO pin 17 during sleep", "d", 17, 17 ], ["S18", "PM GPIO pin 18 during sleep", "d", 18, 18 ], ["S19", "PM GPIO pin 19 during sleep", "d", 19, 19 ], ["S20", "PM GPIO pin 20 during sleep", "d", 20, 20 ], ["S21", "PM GPIO pin 21 during sleep", "d", 21, 21 ], ["S22", "PM GPIO pin 22 during sleep", "d", 22, 22 ], ["S23", "PM GPIO pin 23 during sleep", "d", 23, 23 ], ["S24", "PM GPIO pin 24 during sleep", "d", 24, 24 ], ["S25", "PM GPIO pin 25 during sleep", "d", 25, 25 ], ["S26", "PM GPIO pin 26 during sleep", "d", 26, 26 ], ["S27", "PM GPIO pin 27 during sleep", "d", 27, 27 ], ["S28", "PM GPIO pin 28 during sleep", "d", 28, 28 ], ["S29", "PM GPIO pin 29 during sleep", "d", 29, 29 ], ["S30", "PM GPIO pin 30 during sleep", "d", 30, 30 ], ["S31", "PM GPIO pin 31 during sleep", "d", 31, 31 ],], ], "PGSR1": ["3-29", "Power Manager GPIO Sleep State Register 1", pxa.PGSR1, [ ["S32", "PM GPIO pin 32 during sleep", "d", 0, 0 ], ["S33", "PM GPIO pin 33 during sleep", "d", 1, 1 ], ["S34", "PM GPIO pin 34 during sleep", "d", 2, 2 ], ["S35", "PM GPIO pin 35 during sleep", "d", 3, 3 ], ["S36", "PM GPIO pin 36 during sleep", "d", 4, 4 ], ["S37", "PM GPIO pin 37 during sleep", "d", 5, 5 ], ["S38", "PM GPIO pin 38 during sleep", "d", 6, 6 ], ["S39", "PM GPIO pin 39 during sleep", "d", 7, 7 ], ["S40", "PM GPIO pin 40 during sleep", "d", 8, 8 ], ["S41", "PM GPIO pin 41 during sleep", "d", 9, 9 ], ["S42", "PM GPIO pin 42 during sleep", "d", 10, 10 ], ["S43", "PM GPIO pin 43 during sleep", "d", 11, 11 ], ["S44", "PM GPIO pin 44 during sleep", "d", 12, 12 ], ["S45", "PM GPIO pin 45 during sleep", "d", 13, 13 ], ["S46", "PM GPIO pin 46 during sleep", "d", 14, 14 ], ["S47", "PM GPIO pin 47 during sleep", "d", 15, 15 ], ["S48", "PM GPIO pin 48 during sleep", "d", 16, 16 ], ["S49", "PM GPIO pin 49 during sleep", "d", 17, 17 ], ["S50", "PM GPIO pin 50 during sleep", "d", 18, 18 ], ["S51", "PM GPIO pin 51 during sleep", "d", 19, 19 ], ["S52", "PM GPIO pin 52 during sleep", "d", 20, 20 ], ["S53", "PM GPIO pin 53 during sleep", "d", 21, 21 ], ["S54", "PM GPIO pin 54 during sleep", "d", 22, 22 ], ["S55", "PM GPIO pin 55 during sleep", "d", 23, 23 ], ["S56", "PM GPIO pin 56 during sleep", "d", 24, 24 ], ["S57", "PM GPIO pin 57 during sleep", "d", 25, 25 ], ["S58", "PM GPIO pin 58 during sleep", "d", 26, 26 ], ["S59", "PM GPIO pin 59 during sleep", "d", 27, 27 ], ["S60", "PM GPIO pin 60 during sleep", "d", 28, 28 ], ["S61", "PM GPIO pin 61 during sleep", "d", 29, 29 ], ["S62", "PM GPIO pin 62 during sleep", "d", 30, 30 ], ["S63", "PM GPIO pin 63 during sleep", "d", 31, 31 ],], ], "PGSR2": ["3-30", "Power Manager GPIO Sleep State Register 2", pxa.PGSR2, [ ["S64", "PM GPIO pin 64 during sleep", "d", 0, 0 ], ["S65", "PM GPIO pin 65 during sleep", "d", 1, 1 ], ["S66", "PM GPIO pin 66 during sleep", "d", 2, 2 ], ["S67", "PM GPIO pin 67 during sleep", "d", 3, 3 ], ["S68", "PM GPIO pin 68 during sleep", "d", 4, 4 ], ["S69", "PM GPIO pin 69 during sleep", "d", 5, 5 ], ["S70", "PM GPIO pin 70 during sleep", "d", 6, 6 ], ["S71", "PM GPIO pin 71 during sleep", "d", 7, 7 ], ["S72", "PM GPIO pin 72 during sleep", "d", 8, 8 ], ["S73", "PM GPIO pin 73 during sleep", "d", 9, 9 ], ["S74", "PM GPIO pin 74 during sleep", "d", 10, 10 ], ["S75", "PM GPIO pin 75 during sleep", "d", 11, 11 ], ["S76", "PM GPIO pin 76 during sleep", "d", 12, 12 ], ["S77", "PM GPIO pin 77 during sleep", "d", 13, 13 ], ["S78", "PM GPIO pin 78 during sleep", "d", 14, 14 ], ["S79", "PM GPIO pin 79 during sleep", "d", 15, 15 ], ["S80", "PM GPIO pin 80 during sleep", "d", 16, 16 ],], ], "RCSR": ["3-31", "Power Manager Reset Controller Status Register", pxa.RCSR, [ ["HWR", "PM hardware reset", "ldocc", 0, 0 ], ["WDR", "PM watchdog reset", "ldocc", 1, 1 ], ["SMR", "PM sleep mode", "ldocc", 2, 2 ], ["GFR", "PM GPIO reset", "ldocc", 3, 3 ],], ], "CCCR": ["3-33", "Core Clock Configuration Register", pxa.CCCR, [ ["L", "CM cryst freq to mem freq factor", "lbCCCR_L", 4, 0 ], ["M", "CM mem freq to run freq factor", "lbCCCR_M", 6, 5 ], ["N", "CM run freq to turbo freq factor", "lbCCCR_N", 9, 7 ],], ], "CKEN": ["3-34", "Clock Enable Register", pxa.CKEN, [ ["0", "CM PWM0 clock", "ldena", 0, 0 ], ["1", "CM PWM1 clock", "ldena", 1, 1 ], ["2", "CM AC97 clock", "ldena", 2, 2 ], ["3", "CM SSP clock", "ldena", 3, 3 ], ["5", "CM STUART clock","ldena", 5, 5 ], ["6", "CM FFUART clock","ldena", 6, 6 ], ["7", "CM BTUART clock","ldena", 7, 7 ], ["8", "CM I2S clock", "ldena", 8, 8 ], ["11", "CM USB clock", "ldena", 11, 11 ], ["12", "CM MMC clock", "ldena", 12, 12 ], ["13", "CM FIPC clock", "ldena", 13, 13 ], ["14", "CM I2C clock", "ldena", 14, 14 ], ["16", "CM LCD clock", "ldena", 16, 16 ],], ], "OSCC": ["3-36", "Oscillator Configuration Register", pxa.OSCC, [ ["OOK", "CM 32.768 kHz oscillator stable", "ldena", 0, 0 ], ["OON", "CM 32.768 kHz oscillator write-once", "ldena", 1, 1 ],], ], "GPLR0": ["4-7", "GPIO Pin Level Register 0", pxa.GPLR0, [ ["0", "GPIO pin 0", "d", 0, 0 ], ["1", "GPIO pin 1", "d", 1, 1 ], ["2", "GPIO pin 2", "d", 2, 2 ], ["3", "GPIO pin 3", "d", 3, 3 ], ["4", "GPIO pin 4", "d", 4, 4 ], ["5", "GPIO pin 5", "d", 5, 5 ], ["6", "GPIO pin 6", "d", 6, 6 ], ["7", "GPIO pin 7", "d", 7, 7 ], ["8", "GPIO pin 8", "d", 8, 8 ], ["9", "GPIO pin 9", "d", 9, 9 ], ["10", "GPIO pin 10", "d", 10, 10 ], ["11", "GPIO pin 11", "d", 11, 11 ], ["12", "GPIO pin 12", "d", 12, 12 ], ["13", "GPIO pin 13", "d", 13, 13 ], ["14", "GPIO pin 14", "d", 14, 14 ], ["15", "GPIO pin 15", "d", 15, 15 ], ["16", "GPIO pin 16", "d", 16, 16 ], ["17", "GPIO pin 17", "d", 17, 17 ], ["18", "GPIO pin 18", "d", 18, 18 ], ["19", "GPIO pin 19", "d", 19, 19 ], ["20", "GPIO pin 20", "d", 20, 20 ], ["21", "GPIO pin 21", "d", 21, 21 ], ["22", "GPIO pin 22", "d", 22, 22 ], ["23", "GPIO pin 23", "d", 23, 23 ], ["24", "GPIO pin 24", "d", 24, 24 ], ["25", "GPIO pin 25", "d", 25, 25 ], ["26", "GPIO pin 26", "d", 26, 26 ], ["27", "GPIO pin 27", "d", 27, 27 ], ["28", "GPIO pin 28", "d", 28, 28 ], ["29", "GPIO pin 29", "d", 29, 29 ], ["30", "GPIO pin 30", "d", 30, 30 ], ["31", "GPIO pin 31", "d", 31, 31 ],], ], "GPLR1": ["4-8", "GPIO Pin Level Register 1", pxa.GPLR1, [ ["32", "GPIO pin 32", "d", 0, 0 ], ["33", "GPIO pin 33", "d", 1, 1 ], ["34", "GPIO pin 34", "d", 2, 2 ], ["35", "GPIO pin 35", "d", 3, 3 ], ["36", "GPIO pin 36", "d", 4, 4 ], ["37", "GPIO pin 37", "d", 5, 5 ], ["38", "GPIO pin 38", "d", 6, 6 ], ["39", "GPIO pin 39", "d", 7, 7 ], ["40", "GPIO pin 40", "d", 8, 8 ], ["41", "GPIO pin 41", "d", 9, 9 ], ["42", "GPIO pin 42", "d", 10, 10 ], ["43", "GPIO pin 43", "d", 11, 11 ], ["44", "GPIO pin 44", "d", 12, 12 ], ["45", "GPIO pin 45", "d", 13, 13 ], ["46", "GPIO pin 46", "d", 14, 14 ], ["47", "GPIO pin 47", "d", 15, 15 ], ["48", "GPIO pin 48", "d", 16, 16 ], ["49", "GPIO pin 49", "d", 17, 17 ], ["50", "GPIO pin 50", "d", 18, 18 ], ["51", "GPIO pin 51", "d", 19, 19 ], ["52", "GPIO pin 52", "d", 20, 20 ], ["53", "GPIO pin 53", "d", 21, 21 ], ["54", "GPIO pin 54", "d", 22, 22 ], ["55", "GPIO pin 55", "d", 23, 23 ], ["56", "GPIO pin 56", "d", 24, 24 ], ["57", "GPIO pin 57", "d", 25, 25 ], ["58", "GPIO pin 58", "d", 26, 26 ], ["59", "GPIO pin 59", "d", 27, 27 ], ["60", "GPIO pin 60", "d", 28, 28 ], ["61", "GPIO pin 61", "d", 29, 29 ], ["62", "GPIO pin 62", "d", 30, 30 ], ["63", "GPIO pin 63", "d", 31, 31 ],], ], "GPLR2": ["4-8", "GPIO Pin Level Register 2", pxa.GPLR2, [ ["64", "GPIO pin 64", "d", 0, 0 ], ["65", "GPIO pin 65", "d", 1, 1 ], ["66", "GPIO pin 66", "d", 2, 2 ], ["67", "GPIO pin 67", "d", 3, 3 ], ["68", "GPIO pin 68", "d", 4, 4 ], ["69", "GPIO pin 69", "d", 5, 5 ], ["70", "GPIO pin 70", "d", 6, 6 ], ["71", "GPIO pin 71", "d", 7, 7 ], ["72", "GPIO pin 72", "d", 8, 8 ], ["73", "GPIO pin 73", "d", 9, 9 ], ["74", "GPIO pin 74", "d", 10, 10 ], ["75", "GPIO pin 75", "d", 11, 11 ], ["76", "GPIO pin 76", "d", 12, 12 ], ["77", "GPIO pin 77", "d", 13, 13 ], ["78", "GPIO pin 78", "d", 14, 14 ], ["79", "GPIO pin 79", "d", 15, 15 ], ["80", "GPIO pin 80", "d", 16, 16 ],], ], "GPDR0": ["4-9", "GPIO Pin Direction Register 0", pxa.GPDR0, [ ["0", "GPIO pin 0 i/o direction", "ldoutp", 0, 0 ], ["1", "GPIO pin 1 i/o direction", "ldoutp", 1, 1 ], ["2", "GPIO pin 2 i/o direction", "ldoutp", 2, 2 ], ["3", "GPIO pin 3 i/o direction", "ldoutp", 3, 3 ], ["4", "GPIO pin 4 i/o direction", "ldoutp", 4, 4 ], ["5", "GPIO pin 5 i/o direction", "ldoutp", 5, 5 ], ["6", "GPIO pin 6 i/o direction", "ldoutp", 6, 6 ], ["7", "GPIO pin 7 i/o direction", "ldoutp", 7, 7 ], ["8", "GPIO pin 8 i/o direction", "ldoutp", 8, 8 ], ["9", "GPIO pin 9 i/o direction", "ldoutp", 9, 9 ], ["10", "GPIO pin 10 i/o direction", "ldoutp", 10, 10 ], ["11", "GPIO pin 11 i/o direction", "ldoutp", 11, 11 ], ["12", "GPIO pin 12 i/o direction", "ldoutp", 12, 12 ], ["13", "GPIO pin 13 i/o direction", "ldoutp", 13, 13 ], ["14", "GPIO pin 14 i/o direction", "ldoutp", 14, 14 ], ["15", "GPIO pin 15 i/o direction", "ldoutp", 15, 15 ], ["16", "GPIO pin 16 i/o direction", "ldoutp", 16, 16 ], ["17", "GPIO pin 17 i/o direction", "ldoutp", 17, 17 ], ["18", "GPIO pin 18 i/o direction", "ldoutp", 18, 18 ], ["19", "GPIO pin 19 i/o direction", "ldoutp", 19, 19 ], ["20", "GPIO pin 20 i/o direction", "ldoutp", 20, 20 ], ["21", "GPIO pin 21 i/o direction", "ldoutp", 21, 21 ], ["22", "GPIO pin 22 i/o direction", "ldoutp", 22, 22 ], ["23", "GPIO pin 23 i/o direction", "ldoutp", 23, 23 ], ["24", "GPIO pin 24 i/o direction", "ldoutp", 24, 24 ], ["25", "GPIO pin 25 i/o direction", "ldoutp", 25, 25 ], ["26", "GPIO pin 26 i/o direction", "ldoutp", 26, 26 ], ["27", "GPIO pin 27 i/o direction", "ldoutp", 27, 27 ], ["28", "GPIO pin 28 i/o direction", "ldoutp", 28, 28 ], ["29", "GPIO pin 29 i/o direction", "ldoutp", 29, 29 ], ["30", "GPIO pin 30 i/o direction", "ldoutp", 30, 30 ], ["31", "GPIO pin 31 i/o direction", "ldoutp", 31, 31 ],], ], "GPDR1": ["4-9", "GPIO Pin Direction Register 1", pxa.GPDR1, [ ["32", "GPIO pin 32 i/o direction", "ldoutp", 0, 0 ], ["33", "GPIO pin 33 i/o direction", "ldoutp", 1, 1 ], ["34", "GPIO pin 34 i/o direction", "ldoutp", 2, 2 ], ["35", "GPIO pin 35 i/o direction", "ldoutp", 3, 3 ], ["36", "GPIO pin 36 i/o direction", "ldoutp", 4, 4 ], ["37", "GPIO pin 37 i/o direction", "ldoutp", 5, 5 ], ["38", "GPIO pin 38 i/o direction", "ldoutp", 6, 6 ], ["39", "GPIO pin 39 i/o direction", "ldoutp", 7, 7 ], ["40", "GPIO pin 40 i/o direction", "ldoutp", 8, 8 ], ["41", "GPIO pin 41 i/o direction", "ldoutp", 9, 9 ], ["42", "GPIO pin 42 i/o direction", "ldoutp", 10, 10 ], ["43", "GPIO pin 43 i/o direction", "ldoutp", 11, 11 ], ["44", "GPIO pin 44 i/o direction", "ldoutp", 12, 12 ], ["45", "GPIO pin 45 i/o direction", "ldoutp", 13, 13 ], ["46", "GPIO pin 46 i/o direction", "ldoutp", 14, 14 ], ["47", "GPIO pin 47 i/o direction", "ldoutp", 15, 15 ], ["48", "GPIO pin 48 i/o direction", "ldoutp", 16, 16 ], ["49", "GPIO pin 49 i/o direction", "ldoutp", 17, 17 ], ["50", "GPIO pin 50 i/o direction", "ldoutp", 18, 18 ], ["51", "GPIO pin 51 i/o direction", "ldoutp", 19, 19 ], ["52", "GPIO pin 52 i/o direction", "ldoutp", 20, 20 ], ["53", "GPIO pin 53 i/o direction", "ldoutp", 21, 21 ], ["54", "GPIO pin 54 i/o direction", "ldoutp", 22, 22 ], ["55", "GPIO pin 55 i/o direction", "ldoutp", 23, 23 ], ["56", "GPIO pin 56 i/o direction", "ldoutp", 24, 24 ], ["57", "GPIO pin 57 i/o direction", "ldoutp", 25, 25 ], ["58", "GPIO pin 58 i/o direction", "ldoutp", 26, 26 ], ["59", "GPIO pin 59 i/o direction", "ldoutp", 27, 27 ], ["60", "GPIO pin 60 i/o direction", "ldoutp", 28, 28 ], ["61", "GPIO pin 61 i/o direction", "ldoutp", 29, 29 ], ["62", "GPIO pin 62 i/o direction", "ldoutp", 30, 30 ], ["63", "GPIO pin 63 i/o direction", "ldoutp", 31, 31 ],], ], "GPDR2": ["4-9", "GPIO Pin Direction Register 2", pxa.GPDR2, [ ["64", "GPIO pin 64 i/o direction", "ldoutp", 0, 0 ], ["65", "GPIO pin 65 i/o direction", "ldoutp", 1, 1 ], ["66", "GPIO pin 66 i/o direction", "ldoutp", 2, 2 ], ["67", "GPIO pin 67 i/o direction", "ldoutp", 3, 3 ], ["68", "GPIO pin 68 i/o direction", "ldoutp", 4, 4 ], ["69", "GPIO pin 69 i/o direction", "ldoutp", 5, 5 ], ["70", "GPIO pin 70 i/o direction", "ldoutp", 6, 6 ], ["71", "GPIO pin 71 i/o direction", "ldoutp", 7, 7 ], ["72", "GPIO pin 72 i/o direction", "ldoutp", 8, 8 ], ["73", "GPIO pin 73 i/o direction", "ldoutp", 9, 9 ], ["74", "GPIO pin 74 i/o direction", "ldoutp", 10, 10 ], ["75", "GPIO pin 75 i/o direction", "ldoutp", 11, 11 ], ["76", "GPIO pin 76 i/o direction", "ldoutp", 12, 12 ], ["77", "GPIO pin 77 i/o direction", "ldoutp", 13, 13 ], ["78", "GPIO pin 78 i/o direction", "ldoutp", 14, 14 ], ["79", "GPIO pin 79 i/o direction", "ldoutp", 15, 15 ], ["80", "GPIO pin 80 i/o direction", "ldoutp", 16, 16 ],], ], "GRER0": ["4-13", "GPIO Raising Edge Detect Enable Register 0", pxa.GRER0, [ ["0", "GPIO pin 0 raising edge detect", "ldena", 0, 0 ], ["1", "GPIO pin 1 raising edge detect", "ldena", 1, 1 ], ["2", "GPIO pin 2 raising edge detect", "ldena", 2, 2 ], ["3", "GPIO pin 3 raising edge detect", "ldena", 3, 3 ], ["4", "GPIO pin 4 raising edge detect", "ldena", 4, 4 ], ["5", "GPIO pin 5 raising edge detect", "ldena", 5, 5 ], ["6", "GPIO pin 6 raising edge detect", "ldena", 6, 6 ], ["7", "GPIO pin 7 raising edge detect", "ldena", 7, 7 ], ["8", "GPIO pin 8 raising edge detect", "ldena", 8, 8 ], ["9", "GPIO pin 9 raising edge detect", "ldena", 9, 9 ], ["10", "GPIO pin 10 raising edge detect", "ldena", 10, 10 ], ["11", "GPIO pin 11 raising edge detect", "ldena", 11, 11 ], ["12", "GPIO pin 12 raising edge detect", "ldena", 12, 12 ], ["13", "GPIO pin 13 raising edge detect", "ldena", 13, 13 ], ["14", "GPIO pin 14 raising edge detect", "ldena", 14, 14 ], ["15", "GPIO pin 15 raising edge detect", "ldena", 15, 15 ], ["16", "GPIO pin 16 raising edge detect", "ldena", 16, 16 ], ["17", "GPIO pin 17 raising edge detect", "ldena", 17, 17 ], ["18", "GPIO pin 18 raising edge detect", "ldena", 18, 18 ], ["19", "GPIO pin 19 raising edge detect", "ldena", 19, 19 ], ["20", "GPIO pin 20 raising edge detect", "ldena", 20, 20 ], ["21", "GPIO pin 21 raising edge detect", "ldena", 21, 21 ], ["22", "GPIO pin 22 raising edge detect", "ldena", 22, 22 ], ["23", "GPIO pin 23 raising edge detect", "ldena", 23, 23 ], ["24", "GPIO pin 24 raising edge detect", "ldena", 24, 24 ], ["25", "GPIO pin 25 raising edge detect", "ldena", 25, 25 ], ["26", "GPIO pin 26 raising edge detect", "ldena", 26, 26 ], ["27", "GPIO pin 27 raising edge detect", "ldena", 27, 27 ], ["28", "GPIO pin 28 raising edge detect", "ldena", 28, 28 ], ["29", "GPIO pin 29 raising edge detect", "ldena", 29, 29 ], ["30", "GPIO pin 30 raising edge detect", "ldena", 30, 30 ], ["31", "GPIO pin 31 raising edge detect", "ldena", 31, 31 ],], ], "GRER1": ["4-13", "GPIO Raising Edge Detect Enable Register 1", pxa.GRER1, [ ["32", "GPIO pin 32 raising edge detect", "ldena", 0, 0 ], ["33", "GPIO pin 33 raising edge detect", "ldena", 1, 1 ], ["34", "GPIO pin 34 raising edge detect", "ldena", 2, 2 ], ["35", "GPIO pin 35 raising edge detect", "ldena", 3, 3 ], ["36", "GPIO pin 36 raising edge detect", "ldena", 4, 4 ], ["37", "GPIO pin 37 raising edge detect", "ldena", 5, 5 ], ["38", "GPIO pin 38 raising edge detect", "ldena", 6, 6 ], ["39", "GPIO pin 39 raising edge detect", "ldena", 7, 7 ], ["40", "GPIO pin 40 raising edge detect", "ldena", 8, 8 ], ["41", "GPIO pin 41 raising edge detect", "ldena", 9, 9 ], ["42", "GPIO pin 42 raising edge detect", "ldena", 10, 10 ], ["43", "GPIO pin 43 raising edge detect", "ldena", 11, 11 ], ["44", "GPIO pin 44 raising edge detect", "ldena", 12, 12 ], ["45", "GPIO pin 45 raising edge detect", "ldena", 13, 13 ], ["46", "GPIO pin 46 raising edge detect", "ldena", 14, 14 ], ["47", "GPIO pin 47 raising edge detect", "ldena", 15, 15 ], ["48", "GPIO pin 48 raising edge detect", "ldena", 16, 16 ], ["49", "GPIO pin 49 raising edge detect", "ldena", 17, 17 ], ["50", "GPIO pin 50 raising edge detect", "ldena", 18, 18 ], ["51", "GPIO pin 51 raising edge detect", "ldena", 19, 19 ], ["52", "GPIO pin 52 raising edge detect", "ldena", 20, 20 ], ["53", "GPIO pin 53 raising edge detect", "ldena", 21, 21 ], ["54", "GPIO pin 54 raising edge detect", "ldena", 22, 22 ], ["55", "GPIO pin 55 raising edge detect", "ldena", 23, 23 ], ["56", "GPIO pin 56 raising edge detect", "ldena", 24, 24 ], ["57", "GPIO pin 57 raising edge detect", "ldena", 25, 25 ], ["58", "GPIO pin 58 raising edge detect", "ldena", 26, 26 ], ["59", "GPIO pin 59 raising edge detect", "ldena", 27, 27 ], ["60", "GPIO pin 60 raising edge detect", "ldena", 28, 28 ], ["61", "GPIO pin 61 raising edge detect", "ldena", 29, 29 ], ["62", "GPIO pin 62 raising edge detect", "ldena", 30, 30 ], ["63", "GPIO pin 63 raising edge detect", "ldena", 31, 31 ],], ], "GRER2": ["4-13", "GPIO Raising Edge Detect Enable Register 2", pxa.GRER2, [ ["64", "GPIO pin 64 raising edge detect", "ldena", 0, 0 ], ["65", "GPIO pin 65 raising edge detect", "ldena", 1, 1 ], ["66", "GPIO pin 66 raising edge detect", "ldena", 2, 2 ], ["67", "GPIO pin 67 raising edge detect", "ldena", 3, 3 ], ["68", "GPIO pin 68 raising edge detect", "ldena", 4, 4 ], ["69", "GPIO pin 69 raising edge detect", "ldena", 5, 5 ], ["70", "GPIO pin 70 raising edge detect", "ldena", 6, 6 ], ["71", "GPIO pin 71 raising edge detect", "ldena", 7, 7 ], ["72", "GPIO pin 72 raising edge detect", "ldena", 8, 8 ], ["73", "GPIO pin 73 raising edge detect", "ldena", 9, 9 ], ["74", "GPIO pin 74 raising edge detect", "ldena", 10, 10 ], ["75", "GPIO pin 75 raising edge detect", "ldena", 11, 11 ], ["76", "GPIO pin 76 raising edge detect", "ldena", 12, 12 ], ["77", "GPIO pin 77 raising edge detect", "ldena", 13, 13 ], ["78", "GPIO pin 78 raising edge detect", "ldena", 14, 14 ], ["79", "GPIO pin 79 raising edge detect", "ldena", 15, 15 ], ["80", "GPIO pin 80 raising edge detect", "ldena", 16, 16 ],], ], "GFER0": ["4-14", "GPIO Falling Edge Detect Enable Register 0", pxa.GFER0, [ ["0", "GPIO pin 0 falling edge detect", "ldena", 0, 0 ], ["1", "GPIO pin 1 falling edge detect", "ldena", 1, 1 ], ["2", "GPIO pin 2 falling edge detect", "ldena", 2, 2 ], ["3", "GPIO pin 3 falling edge detect", "ldena", 3, 3 ], ["4", "GPIO pin 4 falling edge detect", "ldena", 4, 4 ], ["5", "GPIO pin 5 falling edge detect", "ldena", 5, 5 ], ["6", "GPIO pin 6 falling edge detect", "ldena", 6, 6 ], ["7", "GPIO pin 7 falling edge detect", "ldena", 7, 7 ], ["8", "GPIO pin 8 falling edge detect", "ldena", 8, 8 ], ["9", "GPIO pin 9 falling edge detect", "ldena", 9, 9 ], ["10", "GPIO pin 10 falling edge detect", "ldena", 10, 10 ], ["11", "GPIO pin 11 falling edge detect", "ldena", 11, 11 ], ["12", "GPIO pin 12 falling edge detect", "ldena", 12, 12 ], ["13", "GPIO pin 13 falling edge detect", "ldena", 13, 13 ], ["14", "GPIO pin 14 falling edge detect", "ldena", 14, 14 ], ["15", "GPIO pin 15 falling edge detect", "ldena", 15, 15 ], ["16", "GPIO pin 16 falling edge detect", "ldena", 16, 16 ], ["17", "GPIO pin 17 falling edge detect", "ldena", 17, 17 ], ["18", "GPIO pin 18 falling edge detect", "ldena", 18, 18 ], ["19", "GPIO pin 19 falling edge detect", "ldena", 19, 19 ], ["20", "GPIO pin 20 falling edge detect", "ldena", 20, 20 ], ["21", "GPIO pin 21 falling edge detect", "ldena", 21, 21 ], ["22", "GPIO pin 22 falling edge detect", "ldena", 22, 22 ], ["23", "GPIO pin 23 falling edge detect", "ldena", 23, 23 ], ["24", "GPIO pin 24 falling edge detect", "ldena", 24, 24 ], ["25", "GPIO pin 25 falling edge detect", "ldena", 25, 25 ], ["26", "GPIO pin 26 falling edge detect", "ldena", 26, 26 ], ["27", "GPIO pin 27 falling edge detect", "ldena", 27, 27 ], ["28", "GPIO pin 28 falling edge detect", "ldena", 28, 28 ], ["29", "GPIO pin 29 falling edge detect", "ldena", 29, 29 ], ["30", "GPIO pin 30 falling edge detect", "ldena", 30, 30 ], ["31", "GPIO pin 31 falling edge detect", "ldena", 31, 31 ],], ], "GFER1": ["4-14", "GPIO Falling Edge Detect Enable Register 1", pxa.GFER1, [ ["32", "GPIO pin 32 falling edge detect", "ldena", 0, 0 ], ["33", "GPIO pin 33 falling edge detect", "ldena", 1, 1 ], ["34", "GPIO pin 34 falling edge detect", "ldena", 2, 2 ], ["35", "GPIO pin 35 falling edge detect", "ldena", 3, 3 ], ["36", "GPIO pin 36 falling edge detect", "ldena", 4, 4 ], ["37", "GPIO pin 37 falling edge detect", "ldena", 5, 5 ], ["38", "GPIO pin 38 falling edge detect", "ldena", 6, 6 ], ["39", "GPIO pin 39 falling edge detect", "ldena", 7, 7 ], ["40", "GPIO pin 40 falling edge detect", "ldena", 8, 8 ], ["41", "GPIO pin 41 falling edge detect", "ldena", 9, 9 ], ["42", "GPIO pin 42 falling edge detect", "ldena", 10, 10 ], ["43", "GPIO pin 43 falling edge detect", "ldena", 11, 11 ], ["44", "GPIO pin 44 falling edge detect", "ldena", 12, 12 ], ["45", "GPIO pin 45 falling edge detect", "ldena", 13, 13 ], ["46", "GPIO pin 46 falling edge detect", "ldena", 14, 14 ], ["47", "GPIO pin 47 falling edge detect", "ldena", 15, 15 ], ["48", "GPIO pin 48 falling edge detect", "ldena", 16, 16 ], ["49", "GPIO pin 49 falling edge detect", "ldena", 17, 17 ], ["50", "GPIO pin 50 falling edge detect", "ldena", 18, 18 ], ["51", "GPIO pin 51 falling edge detect", "ldena", 19, 19 ], ["52", "GPIO pin 52 falling edge detect", "ldena", 20, 20 ], ["53", "GPIO pin 53 falling edge detect", "ldena", 21, 21 ], ["54", "GPIO pin 54 falling edge detect", "ldena", 22, 22 ], ["55", "GPIO pin 55 falling edge detect", "ldena", 23, 23 ], ["56", "GPIO pin 56 falling edge detect", "ldena", 24, 24 ], ["57", "GPIO pin 57 falling edge detect", "ldena", 25, 25 ], ["58", "GPIO pin 58 falling edge detect", "ldena", 26, 26 ], ["59", "GPIO pin 59 falling edge detect", "ldena", 27, 27 ], ["60", "GPIO pin 60 falling edge detect", "ldena", 28, 28 ], ["61", "GPIO pin 61 falling edge detect", "ldena", 29, 29 ], ["62", "GPIO pin 62 falling edge detect", "ldena", 30, 30 ], ["63", "GPIO pin 63 falling edge detect", "ldena", 31, 31 ],], ], "GFER2": ["4-14", "GPIO Falling Edge Detect Enable Register 2", pxa.GFER2, [ ["64", "GPIO pin 64 falling edge detect", "ldena", 0, 0 ], ["65", "GPIO pin 65 falling edge detect", "ldena", 1, 1 ], ["66", "GPIO pin 66 falling edge detect", "ldena", 2, 2 ], ["67", "GPIO pin 67 falling edge detect", "ldena", 3, 3 ], ["68", "GPIO pin 68 falling edge detect", "ldena", 4, 4 ], ["69", "GPIO pin 69 falling edge detect", "ldena", 5, 5 ], ["70", "GPIO pin 70 falling edge detect", "ldena", 6, 6 ], ["71", "GPIO pin 71 falling edge detect", "ldena", 7, 7 ], ["72", "GPIO pin 72 falling edge detect", "ldena", 8, 8 ], ["73", "GPIO pin 73 falling edge detect", "ldena", 9, 9 ], ["74", "GPIO pin 74 falling edge detect", "ldena", 10, 10 ], ["75", "GPIO pin 75 falling edge detect", "ldena", 11, 11 ], ["76", "GPIO pin 76 falling edge detect", "ldena", 12, 12 ], ["77", "GPIO pin 77 falling edge detect", "ldena", 13, 13 ], ["78", "GPIO pin 78 falling edge detect", "ldena", 14, 14 ], ["79", "GPIO pin 79 falling edge detect", "ldena", 15, 15 ], ["80", "GPIO pin 80 falling edge detect", "ldena", 16, 16 ],], ], "GEDR0": ["4-15", "GPIO Edge Detect Register 0", pxa.GEDR0, [ ["0", "GPIO pin 0 edge", "lddet", 0, 0 ], ["1", "GPIO pin 1 edge", "lddet", 1, 1 ], ["2", "GPIO pin 2 edge", "lddet", 2, 2 ], ["3", "GPIO pin 3 edge", "lddet", 3, 3 ], ["4", "GPIO pin 4 edge", "lddet", 4, 4 ], ["5", "GPIO pin 5 edge", "lddet", 5, 5 ], ["6", "GPIO pin 6 edge", "lddet", 6, 6 ], ["7", "GPIO pin 7 edge", "lddet", 7, 7 ], ["8", "GPIO pin 8 edge", "lddet", 8, 8 ], ["9", "GPIO pin 9 edge", "lddet", 9, 9 ], ["10", "GPIO pin 10 edge", "lddet", 10, 10 ], ["11", "GPIO pin 11 edge", "lddet", 11, 11 ], ["12", "GPIO pin 12 edge", "lddet", 12, 12 ], ["13", "GPIO pin 13 edge", "lddet", 13, 13 ], ["14", "GPIO pin 14 edge", "lddet", 14, 14 ], ["15", "GPIO pin 15 edge", "lddet", 15, 15 ], ["16", "GPIO pin 16 edge", "lddet", 16, 16 ], ["17", "GPIO pin 17 edge", "lddet", 17, 17 ], ["18", "GPIO pin 18 edge", "lddet", 18, 18 ], ["19", "GPIO pin 19 edge", "lddet", 19, 19 ], ["20", "GPIO pin 20 edge", "lddet", 20, 20 ], ["21", "GPIO pin 21 edge", "lddet", 21, 21 ], ["22", "GPIO pin 22 edge", "lddet", 22, 22 ], ["23", "GPIO pin 23 edge", "lddet", 23, 23 ], ["24", "GPIO pin 24 edge", "lddet", 24, 24 ], ["25", "GPIO pin 25 edge", "lddet", 25, 25 ], ["26", "GPIO pin 26 edge", "lddet", 26, 26 ], ["27", "GPIO pin 27 edge", "lddet", 27, 27 ], ["28", "GPIO pin 28 edge", "lddet", 28, 28 ], ["29", "GPIO pin 29 edge", "lddet", 29, 29 ], ["30", "GPIO pin 30 edge", "lddet", 30, 30 ], ["31", "GPIO pin 31 edge", "lddet", 31, 31 ],], ], "GEDR1": ["4-16", "GPIO Edge Detect Register 1", pxa.GEDR1, [ ["32", "GPIO pin 32 edge", "lddet", 0, 0 ], ["33", "GPIO pin 33 edge", "lddet", 1, 1 ], ["34", "GPIO pin 34 edge", "lddet", 2, 2 ], ["35", "GPIO pin 35 edge", "lddet", 3, 3 ], ["36", "GPIO pin 36 edge", "lddet", 4, 4 ], ["37", "GPIO pin 37 edge", "lddet", 5, 5 ], ["38", "GPIO pin 38 edge", "lddet", 6, 6 ], ["39", "GPIO pin 39 edge", "lddet", 7, 7 ], ["40", "GPIO pin 40 edge", "lddet", 8, 8 ], ["41", "GPIO pin 41 edge", "lddet", 9, 9 ], ["42", "GPIO pin 42 edge", "lddet", 10, 10 ], ["43", "GPIO pin 43 edge", "lddet", 11, 11 ], ["44", "GPIO pin 44 edge", "lddet", 12, 12 ], ["45", "GPIO pin 45 edge", "lddet", 13, 13 ], ["46", "GPIO pin 46 edge", "lddet", 14, 14 ], ["47", "GPIO pin 47 edge", "lddet", 15, 15 ], ["48", "GPIO pin 48 edge", "lddet", 16, 16 ], ["49", "GPIO pin 49 edge", "lddet", 17, 17 ], ["50", "GPIO pin 50 edge", "lddet", 18, 18 ], ["51", "GPIO pin 51 edge", "lddet", 19, 19 ], ["52", "GPIO pin 52 edge", "lddet", 20, 20 ], ["53", "GPIO pin 53 edge", "lddet", 21, 21 ], ["54", "GPIO pin 54 edge", "lddet", 22, 22 ], ["55", "GPIO pin 55 edge", "lddet", 23, 23 ], ["56", "GPIO pin 56 edge", "lddet", 24, 24 ], ["57", "GPIO pin 57 edge", "lddet", 25, 25 ], ["58", "GPIO pin 58 edge", "lddet", 26, 26 ], ["59", "GPIO pin 59 edge", "lddet", 27, 27 ], ["60", "GPIO pin 60 edge", "lddet", 28, 28 ], ["61", "GPIO pin 61 edge", "lddet", 29, 29 ], ["62", "GPIO pin 62 edge", "lddet", 30, 30 ], ["63", "GPIO pin 63 edge", "lddet", 31, 31 ],], ], "GEDR2": ["4-16", "GPIO Edge Detect Register 2", pxa.GEDR2, [ ["64", "GPIO pin 64 edge", "lddet", 0, 0 ], ["65", "GPIO pin 65 edge", "lddet", 1, 1 ], ["66", "GPIO pin 66 edge", "lddet", 2, 2 ], ["67", "GPIO pin 67 edge", "lddet", 3, 3 ], ["68", "GPIO pin 68 edge", "lddet", 4, 4 ], ["69", "GPIO pin 69 edge", "lddet", 5, 5 ], ["70", "GPIO pin 70 edge", "lddet", 6, 6 ], ["71", "GPIO pin 71 edge", "lddet", 7, 7 ], ["72", "GPIO pin 72 edge", "lddet", 8, 8 ], ["73", "GPIO pin 73 edge", "lddet", 9, 9 ], ["74", "GPIO pin 74 edge", "lddet", 10, 10 ], ["75", "GPIO pin 75 edge", "lddet", 11, 11 ], ["76", "GPIO pin 76 edge", "lddet", 12, 12 ], ["77", "GPIO pin 77 edge", "lddet", 13, 13 ], ["78", "GPIO pin 78 edge", "lddet", 14, 14 ], ["79", "GPIO pin 79 edge", "lddet", 15, 15 ], ["80", "GPIO pin 80 edge", "lddet", 16, 16 ],], ], "GAFR0_L": ["4-17", "GPIO Alternate Function Register 0 Lower", pxa.GAFR0_L, [ ["0", "GPIO 0 alternate function", "x", 1, 0 ], ["1", "GPIO 1 alternate function", "x", 3, 2 ], ["2", "GPIO 2 alternate function", "x", 5, 4 ], ["3", "GPIO 3 alternate function", "x", 7, 6 ], ["4", "GPIO 4 alternate function", "x", 9, 8 ], ["5", "GPIO 5 alternate function", "x", 11, 10 ], ["6", "GPIO 6 alternate function", "x", 13, 12 ], ["7", "GPIO 7 alternate function", "x", 15, 14 ], ["8", "GPIO 8 alternate function", "x", 17, 16 ], ["9", "GPIO 9 alternate function", "x", 19, 18 ], ["10", "GPIO 10 alternate function", "x", 21, 20 ], ["11", "GPIO 11 alternate function", "x", 23, 22 ], ["12", "GPIO 12 alternate function", "x", 25, 24 ], ["13", "GPIO 13 alternate function", "x", 27, 26 ], ["14", "GPIO 14 alternate function", "x", 29, 28 ], ["15", "GPIO 15 alternate function", "x", 31, 30 ],], ], "GAFR0_U": ["4-18", "GPIO Alternate Function Register 0 Upper", pxa.GAFR0_U, [ ["16", "GPIO 16 alternate function", "x", 1, 0 ], ["17", "GPIO 17 alternate function", "x", 3, 2 ], ["18", "GPIO 18 alternate function", "x", 5, 4 ], ["19", "GPIO 19 alternate function", "x", 7, 6 ], ["20", "GPIO 20 alternate function", "x", 9, 8 ], ["21", "GPIO 21 alternate function", "x", 11, 10 ], ["22", "GPIO 22 alternate function", "x", 13, 12 ], ["23", "GPIO 23 alternate function", "x", 15, 14 ], ["24", "GPIO 24 alternate function", "x", 17, 16 ], ["25", "GPIO 25 alternate function", "x", 19, 18 ], ["26", "GPIO 26 alternate function", "x", 21, 20 ], ["27", "GPIO 27 alternate function", "x", 23, 22 ], ["28", "GPIO 28 alternate function", "x", 25, 24 ], ["29", "GPIO 29 alternate function", "x", 27, 26 ], ["30", "GPIO 30 alternate function", "x", 29, 28 ], ["31", "GPIO 31 alternate function", "x", 31, 30 ],], ], "GAFR1_L": ["4-18", "GPIO Alternate Function Register 1 Lower", pxa.GAFR1_L, [ ["32", "GPIO 32 alternate function", "x", 1, 0 ], ["33", "GPIO 33 alternate function", "x", 3, 2 ], ["34", "GPIO 34 alternate function", "x", 5, 4 ], ["35", "GPIO 35 alternate function", "x", 7, 6 ], ["36", "GPIO 36 alternate function", "x", 9, 8 ], ["37", "GPIO 37 alternate function", "x", 11, 10 ], ["38", "GPIO 38 alternate function", "x", 13, 12 ], ["39", "GPIO 39 alternate function", "x", 15, 14 ], ["40", "GPIO 40 alternate function", "x", 17, 16 ], ["41", "GPIO 41 alternate function", "x", 19, 18 ], ["42", "GPIO 42 alternate function", "x", 21, 20 ], ["43", "GPIO 43 alternate function", "x", 23, 22 ], ["44", "GPIO 44 alternate function", "x", 25, 24 ], ["45", "GPIO 45 alternate function", "x", 27, 26 ], ["46", "GPIO 46 alternate function", "x", 29, 28 ], ["47", "GPIO 47 alternate function", "x", 31, 30 ],], ], "GAFR1_U": ["4-19", "GPIO Alternate Function Register 1 Upper", pxa.GAFR1_U, [ ["48", "GPIO 48 alternate function", "x", 1, 0 ], ["49", "GPIO 49 alternate function", "x", 3, 2 ], ["50", "GPIO 50 alternate function", "x", 5, 4 ], ["51", "GPIO 51 alternate function", "x", 7, 6 ], ["52", "GPIO 52 alternate function", "x", 9, 8 ], ["53", "GPIO 53 alternate function", "x", 11, 10 ], ["54", "GPIO 54 alternate function", "x", 13, 12 ], ["55", "GPIO 55 alternate function", "x", 15, 14 ], ["56", "GPIO 56 alternate function", "x", 17, 16 ], ["57", "GPIO 57 alternate function", "x", 19, 18 ], ["58", "GPIO 58 alternate function", "x", 21, 20 ], ["59", "GPIO 59 alternate function", "x", 23, 22 ], ["60", "GPIO 60 alternate function", "x", 25, 24 ], ["61", "GPIO 61 alternate function", "x", 27, 26 ], ["62", "GPIO 62 alternate function", "x", 29, 28 ], ["63", "GPIO 63 alternate function", "x", 31, 30 ],], ], "GAFR2_L": ["4-19", "GPIO Alternate Function Register 2 Lower", pxa.GAFR2_L, [ ["64", "GPIO 64 alternate function", "x", 1, 0 ], ["65", "GPIO 65 alternate function", "x", 3, 2 ], ["66", "GPIO 66 alternate function", "x", 5, 4 ], ["67", "GPIO 67 alternate function", "x", 7, 6 ], ["68", "GPIO 68 alternate function", "x", 9, 8 ], ["69", "GPIO 69 alternate function", "x", 11, 10 ], ["70", "GPIO 70 alternate function", "x", 13, 12 ], ["71", "GPIO 71 alternate function", "x", 15, 14 ], ["72", "GPIO 72 alternate function", "x", 17, 16 ], ["73", "GPIO 73 alternate function", "x", 19, 18 ], ["74", "GPIO 74 alternate function", "x", 21, 20 ], ["75", "GPIO 75 alternate function", "x", 23, 22 ], ["76", "GPIO 76 alternate function", "x", 25, 24 ], ["77", "GPIO 77 alternate function", "x", 27, 26 ], ["78", "GPIO 78 alternate function", "x", 29, 28 ], ["79", "GPIO 79 alternate function", "x", 31, 30 ],], ], "GAFR2_U": ["4-20", "GPIO Alternate Function Register 2 Upper", pxa.GAFR2_U, [ ["80", "GPIO 80 alternate function", "x", 1, 0 ],], ], "ICMR": ["4-24", "Interrupt Controller Mask Register", pxa.ICMR, [ ["IM8", "Pending IRQ 8 (GPIO0)", "ld1unmask", 8, 8 ], ["IM9", "Pending IRQ 9 (GPIO1)", "ld1unmask", 9, 9 ], ["IM10", "Pending IRQ 10 (GPIO2_80)", "ld1unmask", 10, 10 ], ["IM11", "Pending IRQ 11 (USB)", "ld1unmask", 11, 11 ], ["IM12", "Pending IRQ 12 (PMU)", "ld1unmask", 12, 12 ], ["IM13", "Pending IRQ 13 (I2S)", "ld1unmask", 13, 13 ], ["IM14", "Pending IRQ 14 (AC97)", "ld1unmask", 14, 14 ], ["IM17", "Pending IRQ 17 (LCD)", "ld1unmask", 17, 17 ], ["IM18", "Pending IRQ 18 (I2C)", "ld1unmask", 18, 18 ], ["IM19", "Pending IRQ 19 (ICP)", "ld1unmask", 19, 19 ], ["IM20", "Pending IRQ 20 (STUART)", "ld1unmask", 20, 20 ], ["IM21", "Pending IRQ 21 (BTUART)", "ld1unmask", 21, 21 ], ["IM22", "Pending IRQ 22 (FFUART)", "ld1unmask", 22, 22 ], ["IM23", "Pending IRQ 23 (MMC)", "ld1unmask", 23, 23 ], ["IM24", "Pending IRQ 24 (SSP)", "ld1unmask", 24, 24 ], ["IM25", "Pending IRQ 25 (DMA)", "ld1unmask", 25, 25 ], ["IM26", "Pending IRQ 26 (OSMR0)", "ld1unmask", 26, 26 ], ["IM27", "Pending IRQ 27 (OSMR1)", "ld1unmask", 27, 27 ], ["IM28", "Pending IRQ 28 (OSMR2)", "ld1unmask", 28, 28 ], ["IM29", "Pending IRQ 29 (OSMR3)", "ld1unmask", 29, 29 ], ["IM30", "Pending IRQ 30 (RTCCLK)", "ld1unmask", 30, 30 ], ["IM31", "Pending IRQ 31 (RTCALM)", "ld1unmask", 31, 31 ],], ], "ICLR": ["4-24", "Interrupt Controller Level Register", pxa.ICLR, [ ["IL8", "IRQ 8 (GPIO0) routing", "ldfiq", 8, 8 ], ["IL9", "IRQ 9 (GPIO1) routing", "ldfiq", 9, 9 ], ["IL10", "IRQ 10 (GPIO2_80) routing", "ldfiq", 10, 10 ], ["IL11", "IRQ 11 (USB) routing", "ldfiq", 11, 11 ], ["IL12", "IRQ 12 (PMU) routing", "ldfiq", 12, 12 ], ["IL13", "IRQ 13 (I2S) routing", "ldfiq", 13, 13 ], ["IL14", "IRQ 14 (AC97) routing", "ldfiq", 14, 14 ], ["IL17", "IRQ 17 (LCD) routing", "ldfiq", 17, 17 ], ["IL18", "IRQ 18 (I2C) routing", "ldfiq", 18, 18 ], ["IL19", "IRQ 19 (ICP) routing", "ldfiq", 19, 19 ], ["IL20", "IRQ 10 (STUART) routing", "ldfiq", 20, 20 ], ["IL21", "IRQ 21 (BTUART) routing", "ldfiq", 21, 21 ], ["IL22", "IRQ 22 (FFUART) routing", "ldfiq", 22, 22 ], ["IL23", "IRQ 23 (MMC) routing", "ldfiq", 23, 23 ], ["IL24", "IRQ 24 (SSP) routing", "ldfiq", 24, 24 ], ["IL25", "IRQ 25 (DMA) routing", "ldfiq", 25, 25 ], ["IL26", "IRQ 26 (OSMR0) routing", "ldfiq", 26, 26 ], ["IL27", "IRQ 27 (OSMR1) routing", "ldfiq", 27, 27 ], ["IL28", "IRQ 28 (OSMR2) routing", "ldfiq", 28, 28 ], ["IL29", "IRQ 29 (OSMR3) routing", "ldfiq", 29, 29 ], ["IL30", "IRQ 30 (RTCCLK) routing", "ldfiq", 30, 30 ], ["IL31", "IRQ 31 (RTCALM) routing", "ldfiq", 31, 31 ],], ], "ICCR": ["4-25", "Interrupt Controller Control Register", pxa.ICCR, [ ["DIM", "ONLY enabled and unmasked IRQs bring CPU from idle to run", "x", 8, 8 ],], ], "ICIP": ["4-26", "Interrupt Controller IRQ Pending Register", pxa.ICIP, [ ["IP8", "IRQ 8 (GPIO0) pending IRQ", "ldpending", 8, 8 ], ["IP9", "IRQ 9 (GPIO1) pending IRQ", "ldpending", 9, 9 ], ["IP10", "IRQ 10 (GPIO2_80) pending IRQ", "ldpending", 10, 10 ], ["IP11", "IRQ 11 (USB) pending IRQ", "ldpending", 11, 11 ], ["IP12", "IRQ 12 (PMU) pending IRQ", "ldpending", 12, 12 ], ["IP13", "IRQ 13 (I2S) pending IRQ", "ldpending", 13, 13 ], ["IP14", "IRQ 14 (AC97) pending IRQ", "ldpending", 14, 14 ], ["IP17", "IRQ 17 (LCD) pending IRQ", "ldpending", 17, 17 ], ["IP18", "IRQ 18 (I2C) pending IRQ", "ldpending", 18, 18 ], ["IP19", "IRQ 19 (ICP) pending IRQ", "ldpending", 19, 19 ], ["IP20", "IRQ 10 (STUART) pending IRQ", "ldpending", 20, 20 ], ["IP21", "IRQ 21 (BTUART) pending IRQ", "ldpending", 21, 21 ], ["IP22", "IRQ 22 (FFUART) pending IRQ", "ldpending", 22, 22 ], ["IP23", "IRQ 23 (MMC) pending IRQ", "ldpending", 23, 23 ], ["IP24", "IRQ 24 (SSP) pending IRQ", "ldpending", 24, 24 ], ["IP25", "IRQ 25 (DMA) pending IRQ", "ldpending", 25, 25 ], ["IP26", "IRQ 26 (OSMR0) pending IRQ", "ldpending", 26, 26 ], ["IP27", "IRQ 27 (OSMR1) pending IRQ", "ldpending", 27, 27 ], ["IP28", "IRQ 28 (OSMR2) pending IRQ", "ldpending", 28, 28 ], ["IP29", "IRQ 29 (OSMR3) pending IRQ", "ldpending", 29, 29 ], ["IP30", "IRQ 30 (RTCCLK) pending IRQ", "ldpending", 30, 30 ], ["IP31", "IRQ 31 (RTCALM) pending IRQ", "ldpending", 31, 31 ],], ], "ICFP": ["4-26", "Interrupt Controller FIQ Pending Register", pxa.ICFP, [ ["FP8", "FIQ 8 (GPIO0) pending FIQ", "ldpending", 8, 8 ], ["FP9", "FIQ 9 (GPIO1) pending FIQ", "ldpending", 9, 9 ], ["FP10", "FIQ 10 (GPIO2_80) pending FIQ", "ldpending", 10, 10 ], ["FP11", "FIQ 11 (USB) pending FIQ", "ldpending", 11, 11 ], ["FP12", "FIQ 12 (PMU) pending FIQ", "ldpending", 12, 12 ], ["FP13", "FIQ 13 (I2S) pending FIQ", "ldpending", 13, 13 ], ["FP14", "FIQ 14 (AC97) pending FIQ", "ldpending", 14, 14 ], ["FP17", "FIQ 17 (LCD) pending FIQ", "ldpending", 17, 17 ], ["FP18", "FIQ 18 (I2C) pending FIQ", "ldpending", 18, 18 ], ["FP19", "FIQ 19 (ICP) pending FIQ", "ldpending", 19, 19 ], ["FP20", "FIQ 10 (STUART) pending FIQ", "ldpending", 20, 20 ], ["FP21", "FIQ 21 (BTUART) pending FIQ", "ldpending", 21, 21 ], ["FP22", "FIQ 22 (FFUART) pending FIQ", "ldpending", 22, 22 ], ["FP23", "FIQ 23 (MMC) pending FIQ", "ldpending", 23, 23 ], ["FP24", "FIQ 24 (SSP) pending FIQ", "ldpending", 24, 24 ], ["FP25", "FIQ 25 (DMA) pending FIQ", "ldpending", 25, 25 ], ["FP26", "FIQ 26 (OSMR0) pending FIQ", "ldpending", 26, 26 ], ["FP27", "FIQ 27 (OSMR1) pending FIQ", "ldpending", 27, 27 ], ["FP28", "FIQ 28 (OSMR2) pending FIQ", "ldpending", 28, 28 ], ["FP29", "FIQ 29 (OSMR3) pending FIQ", "ldpending", 29, 29 ], ["FP30", "FIQ 30 (RTCCLK) pending FIQ", "ldpending", 30, 30 ], ["FP31", "FIQ 31 (RTCALM) pending FIQ", "ldpending", 31, 31 ],], ], "ICPR": ["4-27", "Interrupt Controller Pending Register", pxa.ICPR, [ ["IS8", "IRQ 8 (GPIO0) pending", "ldpending", 8, 8 ], ["IS9", "IRQ 9 (GPIO1) pending", "ldpending", 9, 9 ], ["IS10", "IRQ 10 (GPIO2_80) pending", "ldpending", 10, 10 ], ["IS11", "IRQ 11 (USB) pending", "ldpending", 11, 11 ], ["IS12", "IRQ 12 (PMU) pending", "ldpending", 12, 12 ], ["IS13", "IRQ 13 (I2S) pending", "ldpending", 13, 13 ], ["IS14", "IRQ 14 (AC97) pending", "ldpending", 14, 14 ], ["IS17", "IRQ 17 (LCD) pending", "ldpending", 17, 17 ], ["IS18", "IRQ 18 (I2C) pending", "ldpending", 18, 18 ], ["IS19", "IRQ 19 (ICP) pending", "ldpending", 19, 19 ], ["IS20", "IRQ 10 (STUART) pending", "ldpending", 20, 20 ], ["IS21", "IRQ 21 (BTUART) pending", "ldpending", 21, 21 ], ["IS22", "IRQ 22 (FFUART) pending", "ldpending", 22, 22 ], ["IS23", "IRQ 23 (MMC) pending", "ldpending", 23, 23 ], ["IS24", "IRQ 24 (SSP) pending", "ldpending", 24, 24 ], ["IS25", "IRQ 25 (DMA) pending", "ldpending", 25, 25 ], ["IS26", "IRQ 26 (OSMR0) pending", "ldpending", 26, 26 ], ["IS27", "IRQ 27 (OSMR1) pending", "ldpending", 27, 27 ], ["IS28", "IRQ 28 (OSMR2) pending", "ldpending", 28, 28 ], ["IS29", "IRQ 29 (OSMR3) pending", "ldpending", 29, 29 ], ["IS30", "IRQ 30 (RTCCLK) pending", "ldpending", 30, 30 ], ["IS31", "IRQ 31 (RTCALM) pending", "ldpending", 31, 31 ],], ], "RTTR": ["4-32", "RTC Trim Register", pxa.RTTR, [ ["CK_DIV", "RTC Clock Divider Count", "x", 15, 0 ], ["DEL", "RTC Trim delete Count", "x", 25, 16 ], ["LCK", "RTC Locking for RTTR", "x", 31, 31 ],], ], "RTAR": ["4-32", "RTC Alarm Register", pxa.RTAR, [], ], "RCNR": ["4-33", "RTC Counter Register", pxa.RCNR, [], ], "RTSR": ["4-34", "RTC Status Register", pxa.RTSR, [ ["AL", "RTC Alarm Interrupt detected", "x", 0, 0 ], ["HZ", "RTC Hz Interrupt detected", "x", 1, 1 ], ["ALE", "RTC Alarm Interrupt Enable", "x", 2, 2 ], ["HZE", "RTC Hz Interrupt Enable", "x", 3, 3 ],], ], "OSMR0": ["4-38", "OS Timer Match Register 0", pxa.OSMR0, [], ], "OSMR1": ["4-38", "OS Timer Match Register 1", pxa.OSMR1, [], ], "OSMR2": ["4-38", "OS Timer Match Register 2", pxa.OSMR2, [], ], "OSMR3": ["4-38", "OS Timer Match Register 3", pxa.OSMR3, [], ], "OIER": ["4-39", "OS Timer Interrupt Enable Register", pxa.OIER, [ ["E0", "OS Interrupt for OSMR0 enabled", "x", 0, 0 ], ["E1", "OS Interrupt for OSMR1 enabled", "x", 1, 1 ], ["E2", "OS Interrupt for OSMR2 enabled", "x", 2, 2 ], ["E3", "OS Interrupt for OSMR3 enabled", "x", 3, 3 ],], ], # "WMER": ["4-39", "OS Timer Watchdog Match Enable Register", pxa.WMER, [ # ["WME", "OSMR3 match causes a reset", "x", 0, 0 ],], ], "OSCR": ["4-40", "OS Timer Count Register", pxa.OSCR, [], ], "OSSR": ["4-41", "OS Timer Status Register", pxa.OSSR, [ ["M0", "OS OSMR0 matched OSCR0", "x", 0, 0 ], ["M1", "OS OSMR1 matched OSCR1", "x", 1, 1 ], ["M2", "OS OSMR2 matched OSCR2", "x", 2, 2 ], ["M3", "OS OSMR3 matched OSCR3", "x", 3, 3 ],], ], "PWM_CTRL0": ["4-45", "PWM Control Register 0", pxa.PWM_CTRL0, [ ["PRESCALE", "PWM0 Prescale Divisor", "d", 5, 0 ], ["SD", "PWM0 abrupt shutdown", "x", 5, 5 ],], ], "PWM_PWDUTY0": ["4-46", "PWM Duty Cycle Register 0", pxa.PWM_PWDUTY0, [ ["DCYCLE", "PWM0 Duty Cycle", "d", 9, 0 ], ["FDCYCLE", "PWM_OUT0 is set high and does not toggle", "x", 10, 10 ],], ], "PWM_PERVAL0": ["4-47", "PWM Period Control Register 0", pxa.PWM_PERVAL0, [ ["PV", "PWM0 Period Cycle Length", "d", 9, 0 ],], ], "PWM_CTRL1": ["4-45", "PWM Control Register 1", pxa.PWM_CTRL1, [ ["PRESCALE", "PWM1 Prescale Divisor", "d", 5, 0 ], ["SD", "PWM1 abrupt shutdown", "x", 5, 5 ],], ], "PWM_PWDUTY1": ["4-46", "PWM Duty Cycle Register 1", pxa.PWM_PWDUTY1, [ ["DCYCLE", "PWM1 Duty Cycle", "d", 9, 0 ], ["FDCYCLE", "PWM_OUT1 is set high and does not toggle", "x", 10, 10 ],], ], "PWM_PERVAL1": ["4-47", "PWM Period Control Register 1", pxa.PWM_PERVAL1, [ ["PV", "PWM1 Period Cycle Length", "d", 9, 0 ],], ], "LCCR0": ["7-19", "LCD Controller Control Register 0", pxa.LCCR0, [ ["ENB", "LCD controller enable", "d", 0, 0 ], ["CMS", "LCD monochrome operation enable", "d", 1, 1 ], ["SDS", "LCD dual panel display enable", "d", 2, 2 ], ["LDM", "LCD disable done IRQ disable", "d", 3, 3 ], ["SFM", "LCD start of frame IRQ disable", "d", 4, 4 ], ["IUM", "LCD fifo underrun error IRQ disable", "d", 5, 5 ], ["EFM", "LCD end of frame IRQ disable", "d", 6, 6 ], ["PAS", "LCD active display enable", "d", 7, 7 ], ["DPD", "LCD send 8 pixel on L_DD[7:0] at each clock", "d", 9, 9 ], ["DIS", "LCD controller disable", "d", 10, 10 ], ["QDM", "LCD quick disable IRQ disable", "d", 11, 11 ], ["PDD", "LCD palette DMA request delay", "d", 19, 12 ], ["BM", "LCD branch start IRQ disable", "d", 20, 20 ], ["OUM", "LCD fifo underrun IRQ disable", "d", 21, 21 ],], ], "LCCR1": ["7-27", "LCD Controller Control Register 1", pxa.LCCR1, [ ["PPL", "LCD pixels per line (+1)", "d", 9, 0 ], ["HSW", "LCD horizontal sync pulse width (+1)", "d", 10, 10 ], ["ELW", "LCD end of line pixel clock wait count (+1)", "d", 23, 16 ], ["BLW", "LCD beginning of line pixel clock wait count (+1)", "d", 31, 24 ],], ], "LCCR2": ["7-30", "LCD Controller Control Register 2", pxa.LCCR2, [ ["LPP", "LCD lines per panel (+1)", "d", 9, 0 ], ["VSW", "LCD vertical sync pulse width (+1)", "d", 10, 10 ], ["EFW", "LCD end of frame line clock wait count (+1)", "d", 23, 16 ], ["BFW", "LCD beginning of frame line clock wait count (+1)", "d", 31, 24 ],], ], "LCCR3": ["7-32", "LCD Controller Control Register 3", pxa.LCCR3, [ ["PCD", "LCD pixel clock divisor (+1)", "d", 7, 0 ], ["ACB", "LCD AC bias pin frequency (+1)", "d", 15, 8 ], ["API", "LCD AC bias pin transitions per interrupt", "d", 19, 16 ], ["VSP", "LCD L_FCLK vertical sync polarity active low", "d", 20, 20 ], ["HSP", "LCD L_LCLK horizontal sync polarity active low", "d", 21, 21 ], ["PCP", "LCD data sampled on falling edge of L_PCLK", "d", 22, 22 ], ["OEP", "LCD L_BIAS output enable active low", "d", 23, 23 ], ["BPP", "LCD bits per pixel", "<", 26, 24 ], ["DPC", "LCD double pixel clock rate at L_PCLK", "d", 29, 27 ],], ], "MDCNFG": ["6-10", "SDRAM Configuration Register", pxa.MDCNFG, [ ["DE0", "SDRAM enable for partition 0", "d", 0, 0 ], ["DE1", "SDRAM enable for partition 1", "d", 1, 1 ], ["DWID0", "SDRAM data width (0=32, 1=16)", "d", 2, 2 ], ["DCAC0", "Column address bits for partition pair 0/1", "d", 4, 3 ], ["DRAC0", "Row address bits for partition pair 0/1", "d", 6, 5 ], ["DNB0", "Banks in partition pair 0/1 (0=2, 1=4)", "d", 7, 7 ], ["DTC0", "Timing Category for partition pair 0/1", "d", 9, 8 ], ["DADDR0", "Use alternate addressing for partition pair 0/1", "d", 10, 10 ], ["DLATCH0", "Return data latching scheme for partition pair 0/1", "d", 11, 11 ], ["DSA11110", "use SA1111 address muxing for partition pair 0/1", "d", 12, 12 ], ["DE2", "SDRAM enable for partition 2", "d", 16, 16 ], ["DE3", "SDRAM enable for partition 3", "d", 17, 17 ], ["DWID2", "SDRAM data width (0=32, 1=16)", "d", 18, 18 ], ["DCAC2", "Column address bits for partition pair 2/3", "d", 20, 19 ], ["DRAC2", "Row address bits for partition pair 2/3", "d", 22, 21 ], ["DNB2", "Banks in partition pair 2/3 (0=2, 1=4)", "d", 23, 23 ], ["DTC2", "Timing Category for partition pair 2/3", "d", 25, 24 ], ["DADDR2", "Use alternate addressing for partition pair 2/3", "d", 26, 26 ], ["DLATCH2", "Return data latching scheme for partition pair 2/3", "d", 27, 27 ], ["DSA11112", "use SA1111 address muxing for partition pair 2/3", "d", 28, 28 ],], ], "MDMRS": ["6-13", "SDRAM Mode Register Set Configuration Register", pxa.MDMRS, [ ["MDBL0", "SDRAM Partition 0/1 burst length", "x", 2, 0 ], ["MDADD0", "SDRAM Partition 0/1 burst type", "x", 3, 3 ], ["MDCL0", "SDRAM Partition 0/1 CAS latency", "x", 6, 4 ], ["MDMRS0", "MRS value to be written to SDRAM Partition 0/1", "x", 14, 7 ], ["MDBL2", "SDRAM Partition 2/3 burst length", "x", 18, 16 ], ["MDADD2", "SDRAM Partition 2/3 burst type", "x", 19, 19 ], ["MDCL2", "SDRAM Partition 2/3 CAS latency", "x", 22, 20 ], ["MDMRS2", "MRS value to be written to SDRAM Partition 2/3", "x", 30, 23 ],], ], "MDREFR": ["6-15", "SDRAM Refresh Configuration Register", pxa.MDREFR, [ ["DRI", "SDRAM Refresh intervall, all paritions", "x", 11, 0 ], ["E0PIN", "SDRAM Clock Enable Pin 0 Level", "x", 12, 12 ], ["K0RUN", "SDRAM Clock Run Pin 0", "x", 13, 13 ], ["K0DB2", "SDRAM Clock Pin 0 Divide/2", "x", 14, 14 ], ["E1PIN", "SDRAM Clock Enable Pin 1 Level", "x", 15, 15 ], ["K1RUN", "SDRAM Clock Run Pin 1", "x", 16, 16 ], ["K1DB2", "SDRAM Clock Pin 1 Divide/2", "x", 17, 17 ], ["K2RUN", "SDRAM Clock Run Pin 2", "x", 18, 18 ], ["K2DB2", "SDRAM Clock Pin 2 Divide/2", "x", 19, 19 ], ["APD", "SDRAM Auto Power Down enable", "x", 20, 20 ], ["SLFRSH", "SDRAM Self-Refresh", "x", 22, 22 ], ["K0FREE", "SDRAM Free Running Control for SDCLK0", "x", 23, 23 ], ["K1FREE", "SDRAM Free Running Control for SDCLK1", "x", 24, 24 ], ["K2FREE", "SDRAM Free Running Control for SDCLK2", "x", 25, 25 ],], ], "MSC0": ["6-44", "Asynchronous Static Memory Control Register 0", pxa.MSC0, [ ["RT0", "nCS[0] ROM Type", "d", 2, 0 ], ["RBW0", "nCS[0] ROM Bus Width (1=16bit)", "d", 3, 3 ], ["RDF0", "nCS[0] ROM Delay First Access", "d", 7, 4 ], ["RDN0", "nCS[0] ROM Delay Next Access", "d", 11, 8 ], ["RRR0", "nCS[0] ROM/SRAM Recovery Time", "d", 14, 12 ], ["RBUFF0", "nCS[0] Return Buffer Behavior (1=streaming)", "d", 15, 15 ], ["RT1", "nCS[1] ROM Type", "d", 18, 16 ], ["RBW1", "nCS[1] ROM Bus Width (1=16bit)", "d", 19, 19 ], ["RDF1", "nCS[1] ROM Delay First Access", "d", 23, 20 ], ["RDN1", "nCS[1] ROM Delay Next Access", "d", 27, 24 ], ["RRR1", "nCS[1] ROM/SRAM Recovery Time", "d", 30, 28 ], ["RBUFF1", "nCS[1] Return Buffer Behavior (1=streaming)", "d", 31, 31 ],], ], "MSC1": ["6-44", "Asynchronous Static Memory Control Register 1", pxa.MSC1, [ ["RT2", "nCS[2] ROM Type", "d", 2, 0 ], ["RBW2", "nCS[2] ROM Bus Width (1=16bit)", "d", 3, 3 ], ["RDF2", "nCS[2] ROM Delay First Access", "d", 7, 4 ], ["RDN2", "nCS[2] ROM Delay Next Access", "d", 11, 8 ], ["RRR2", "nCS[2] ROM/SRAM Recovery Time", "d", 14, 12 ], ["RBUFF2", "nCS[2] Return Buffer Behavior (1=streaming)", "d", 15, 15 ], ["RT3", "nCS[3] ROM Type", "d", 18, 16 ], ["RBW3", "nCS[3] ROM Bus Width (1=16bit)", "d", 19, 19 ], ["RDF3", "nCS[3] ROM Delay First Access", "d", 23, 20 ], ["RDN3", "nCS[3] ROM Delay Next Access", "d", 27, 24 ], ["RRR3", "nCS[3] ROM/SRAM Recovery Time", "d", 30, 28 ], ["RBUFF3", "nCS[3] Return Buffer Behavior (1=streaming)", "d", 31, 31 ],], ], "MSC2": ["6-44", "Asynchronous Static Memory Control Register 2", pxa.MSC2, [ ["RT4", "nCS[4] ROM Type", "d", 2, 0 ], ["RBW4", "nCS[4] ROM Bus Width (1=16bit)", "d", 3, 3 ], ["RDF4", "nCS[4] ROM Delay First Access", "d", 7, 4 ], ["RDN4", "nCS[4] ROM Delay Next Access", "d", 11, 8 ], ["RRR4", "nCS[4] ROM/SRAM Recovery Time", "d", 14, 12 ], ["RBUFF4", "nCS[4] Return Buffer Behavior (1=streaming)", "d", 15, 15 ], ["RT5", "nCS[5] ROM Type", "d", 18, 16 ], ["RBW5", "nCS[5] ROM Bus Width (1=16bit)", "d", 19, 19 ], ["RDF5", "nCS[5] ROM Delay First Access", "d", 23, 20 ], ["RDN5", "nCS[5] ROM Delay Next Access", "d", 27, 24 ], ["RRR5", "nCS[5] ROM/SRAM Recovery Time", "d", 30, 28 ], ["RBUFF5", "nCS[5] Return Buffer Behavior (1=streaming)", "d", 31, 31 ],], ], "MECR": ["6-60", "Expansion Memory Configuration Register", pxa.MECR, [ ["NOS", "Number of Sockets (1=2 Sockets)", "x", 0, 0 ], ["CIT", "Card inserted", "x", 1, 1 ],], ], "SXCNFG": ["6-31", "Synchronous Static Memory Configuration Register", pxa.SXCNFG, [ ["SXEN0", "Partition 0 enabled as SX memory", "x", 0, 0 ], ["SXEN1", "Partition 1 enabled as SX memory", "x", 1, 1 ], ["SXCL0", "Partition 0/1 CAS Latency", "x", 4, 2 ], ["SXRL0", "Partition 0/1 RAS Latency", "x", 7, 5 ], ["SXRA0", "Partition 0/1 row address bit count", "x", 9, 8 ], ["SXCA0", "Partition 0/1 column address bit count", "x", 11, 10 ], ["SXTP0", "Partition 0/1 memory type", "x", 13, 12 ], ["SXLATCH0", "Partition 0/1 return data with return clock", "x", 14, 14 ], ["SXEN2", "Partition 2 enabled as SX memory", "x", 16, 16 ], ["SXEN3", "Partition 3 enabled as SX memory", "x", 17, 17 ], ["SXCL2", "Partition 2/3 CAS Latency", "x", 20, 18 ], ["SXRL2", "Partition 2/3 RAS Latency", "x", 23, 21 ], ["SXRA2", "Partition 2/3 row address bit count", "x", 25, 24 ], ["SXCA2", "Partition 2/3 column address bit count", "x", 27, 26 ], ["SXTP2", "Partition 2/3 memory type", "x", 29, 28 ], ["SXLATCH2", "Partition 2/3 return data with return clock", "x", 30, 30 ],], ], "SXMRS": ["", "MRS value to be written to SX Memory", pxa.SXMRS, [], ], "MCMEM0": ["6-57", "MEM Control for PCMCIA Socket 0", pxa.MCMEM0, [ ["SET", "Address set time", "d", 6, 0 ], ["ASST", "Command assertion time", "d", 11, 7 ], ["HOLD", "Address hold time", "d", 19, 14 ],], ], "MCMEM1": ["6-57", "MEM Control for PCMCIA Socket 1", pxa.MCMEM1, [ ["SET", "Address set time", "d", 6, 0 ], ["ASST", "Command assertion time", "d", 11, 7 ], ["HOLD", "Address hold time", "d", 19, 14 ],], ], "MCATT0": ["6-58", "ATT Control for PCMCIA Socket 0", pxa.MCATT0, [ ["SET", "Address set time", "d", 6, 0 ], ["ASST", "Command assertion time", "d", 11, 7 ], ["HOLD", "Address hold time", "d", 19, 14 ],], ], "MCATT1": ["6-58", "ATT Control for PCMCIA Socket 1", pxa.MCATT1, [ ["SET", "Address set time", "d", 6, 0 ], ["ASST", "Command assertion time", "d", 11, 7 ], ["HOLD", "Address hold time", "d", 19, 14 ],], ], "MCIO0": ["6-58", "I/O Control for PCMCIA Socket 0", pxa.MCIO0, [ ["SET", "Address set time", "d", 6, 0 ], ["ASST", "Command assertion time", "d", 11, 7 ], ["HOLD", "Address hold time", "d", 19, 14 ],], ], "MCIO1": ["6-58", "I/O Control for PCMCIA Socket 1", pxa.MCIO1, [ ["SET", "Address set time", "d", 6, 0 ], ["ASST", "Command assertion time", "d", 11, 7 ], ["HOLD", "Address hold time", "d", 19, 14 ],], ], "MDMRS": ["", "", pxa.MDMRS, [], ], "BOOT_DEF": ["6-72", "Boot Time Defaults", pxa.BOOT_DEF, [ ["BOOT_SEL", "Boot Configuration at BOOT_SEL pins", "x", 2, 0 ], ["PKG_TYPE", "Processor type, 1 for PXA250", "x", 3, 3 ],], ], "MMC_STRPCL": ["15-23", "MMC Start/Stop Clock", pxa.MMC_STRPCL, [], ], "MMC_STAT": ["15-24", "MMC Status Register", pxa.MMC_STAT, [ ["READ_TIME_OUT", "Read Time Out", "x", 0, 0 ], ["TIME_OUT_RESP", "Time Out Response", "x", 1, 1 ], ["CRC_WRITE_ERROR", "CRC Write Error", "x", 2, 2 ], ["CRC_READ_ERR", "CRC Read Error", "x", 3, 3 ], ["SPI_READ_ERR_TKN", "SPI Read Error Token", "x", 4, 4 ], ["RES_CRC_ERR", "Response CRC Error", "x", 5, 5 ], ["XMIT_FIFO_EMPTY", "Transmit FIFO Empty", "x", 6, 6 ], ["RECV_FIFO_EMPTY", "Receive FIFO Empty", "x", 7, 7 ], ["CLK_EN", "Clock Enabled", "x", 8, 8 ], ["DATA_TRAN_DONE", "Data Transmission Done", "x", 11, 11 ], ["PRG_DONE", "Program Done", "x", 12, 12 ], ["END_CMD_RES", "End Command Response", "x", 13, 13 ], ], ], } lookups = { '0ena': {0:'enabled', 1:'disabled'}, 'ena': {0:'disabled', 1:'enabled'}, 'det': {0:'not detected', 1:'detected'}, 'occ': {0:'not occured', 1:'occured'}, 'outp': {0:'input', 1:'output'}, '1unmask': {0:'masked', 1:'unmasked'}, 'fiq': {0:'IRQ', 1:'FIQ'}, 'pending': {0:'not pending', 1:'pending'}, 'CCCR_L': {1:'99.53MHz', 2:'117.96MHz', 3:'132.171MHz', 4:'147.46MHz', 5:'165.89MHz'}, 'CCCR_M': {1:'Run Freq == Mem Freq', 2:'Run Freq == Mem Freq * 2'}, 'CCCR_N': {2:'Turbo Freq = Run Freq * 1', 3:'Turbo Freq = Run Freq * 1.5', 4:'Turbo Freq = Run Freq * 2', 6:'Turbo Freq = Run Freq * 3'}, } def to_bin(b,n): s = '' for j in range(n): if b & (1<<(n-j-1)): s = s + '1' else: s = s + '0' return s def show_reg(name,reg,mem): print "%-7s %-6s x x %s" % ( name, reg[0], reg[2], mem, reg[1]) for j in range(len(reg[3])): val = reg[3][j] mymem = (mem >> val[4]) & (1 << (val[3]-val[4]+1))-1 desc = '' fmt = val[2] s = '?'+fmt+'?' if fmt[0] == 'l': try: desc = lookups[fmt[2:]][mymem] except KeyError: desc = 'value not in lookup table' fmt = fmt[1] if fmt == 'd': s = '%d' % mymem elif fmt == 'x': s = '%x' % mymem elif fmt == 'x2': s = 'x' % mymem elif fmt == 'x4': s = 'x' % mymem elif fmt == 'x8': s = 'x' % mymem elif fmt == 'b': s = to_bin(mymem, val[3]-val[4]+1) s = " %-8s %s %s" % (s, val[0], val[1]) if desc != '': s = "%-68s %s" % (s, desc) print s first = 1 # only display warning on first occurence def show_reg_from_bdi(name): try: reg = regs[name] except KeyError: print "Register '%s' does not exist" % name sys.exit(1) try: mem = bdi.getlong(reg[2]) except NameError: global first if first: print "You need the bdi python module to communicate with via the BDI 2000 with your board\n" first = 0 mem = 0 show_reg(name, reg, mem) def show_all_from_bdi(): k = regs.keys() k.sort() for name in k: show_reg_from_bdi(name) def usage(): print "Usage: pxarags [register] [value]" sys.exit(1) if __name__ == '__main__': import getopt try: opts, args = getopt.getopt(sys.argv[1:], "h", ["help"]) except getopt.GetoptError: usage(1) for o, a in opts: if o in ("-h", "--help"): usage(0) if len(args) == 0: show_all_from_bdi() sys.exit(0) if len(args) == 1: show_reg_from_bdi(args[0].upper()) sys.exit(0) if len(args) == 2: name = args[0].upper() try: reg = regs[name] except KeyError: print "Register '%s' does not exist" % name sys.exit(1) show_reg(name, reg, eval(args[1])) sys.exit(0) usage()