#!/usr/bin/perl -w
#
# Copyright (C) 2002 M&N Logistik-Lösungen Online GmbH
# written by H.Schurig
# Released unter the GNU GPL, comes as-is, without any warranty
#
use strict;
#my ($msc0, $msc1, $msc2, $mecr, $mcmem0, $mcmem1, $mcatt0, $mcatt1, $mcio0, $mcio1, $mdrefr, $mdcnfg, $mdmrs);
sub ShowReg($$$)
{
my ($reg, $val, $page) = @_;
printf "%-8s 0xx = ", $reg . ':', $val;
my $i = 31;
my $mask = 0x80000000;
while ($i>=0) {
print $val & $mask ? '1' : '0';
print " " if $i == 8;
print " " if $i == 16;
print " " if $i == 24;
$i--;
$mask = $mask >> 1;
}
print " (Page $page)\n";
}
sub ShowMSC($$$)
{
my ($msc0, $msc1, $msc2) = @_;
ShowReg('MSC0', $msc0, '6-44');
ShowReg('MSC1', $msc1, '6-44');
ShowReg('MSC2', $msc2, '6-44');
printf "%-30s M M M M M M\n", "Chip Select", 0,1,2,3,4,5;
printf "%-30s %4s %4s %4s %4s %4s %4s\n",
"Usage", "Flsh", "?", "?", "?", "Ctrl", "I/O";
printf "%-30s M M M M M M\n",
"RT: rom type",
($msc0 ) & 0x7,
($msc0 >> 16) & 0x7,
($msc1 ) & 0x7,
($msc1 >> 16) & 0x7,
($msc2 ) & 0x7,
($msc2 >> 16) & 0x7;
printf "%-30s M M M M M M\n",
"RBW: rom bus width",
(($msc0 >> (3 )) & 1) ? 16 : 32,
(($msc0 >> (3+16)) & 1) ? 16 : 32,
(($msc1 >> (3 )) & 1) ? 16 : 32,
(($msc1 >> (3+16)) & 1) ? 16 : 32,
(($msc2 >> (3 )) & 1) ? 16 : 32,
(($msc2 >> (3+16)) & 1) ? 16 : 32;
printf "%-30s M M M M M M\n",
"RDF: rom delay first access",
($msc0 >> (4 )) & 0xf,
($msc0 >> (4+16)) & 0xf,
($msc1 >> (4 )) & 0xf,
($msc1 >> (4+16)) & 0xf,
($msc2 >> (4 )) & 0xf,
($msc2 >> (4+16)) & 0xf;
printf "%-30s M M M M M M\n",
"RDN: rom delay next access",
($msc0 >> (8 )) & 0xf,
($msc0 >> (8+16)) & 0xf,
($msc1 >> (8 )) & 0xf,
($msc1 >> (8+16)) & 0xf,
($msc2 >> (8 )) & 0xf,
($msc2 >> (8+16)) & 0xf;
printf "%-30s M M M M M M\n",
"RRR: rom/sram recovery time",
($msc0 >> (12 )) & 7,
($msc0 >> (12+16)) & 7,
($msc1 >> (12 )) & 7,
($msc1 >> (12+16)) & 7,
($msc2 >> (12 )) & 7,
($msc2 >> (12+16)) & 7;
printf "%-30s %4s %4s %4s %4s %4s %4s\n",
"RBUFF: buffer type",
(($msc0 >> (15 )) & 1) ? "str" : "buf",
(($msc0 >> (15+16)) & 1) ? "str" : "buf",
(($msc1 >> (15 )) & 1) ? "str" : "buf",
(($msc1 >> (15+16)) & 1) ? "str" : "buf",
(($msc2 >> (15 )) & 1) ? "str" : "buf",
(($msc2 >> (15+16)) & 1) ? "str" : "buf";
}
sub ShowMSC0($)
{
my $msc0 = shift;
ShowReg('MSC0', $msc0, '6-44');
print " - RT0: rom type: ", $msc0 & 0x7, "\n";
print " - RBW0: bus width: ", (($msc0 >> 3) & 1) ? "16" : "32", " bits\n";
print " - RDF0: rom delay first access: ", ($msc0 >> 4) & 0xf, "\n";
print " - RDN0: rom delay next access: ", ($msc0 >> 8) & 0xf, "\n";
print " - RRR0: rom/sram recovery time: ", ($msc0 >> 12) & 7, "\n";
print " - RBUFF0: return data: ", (($msc0 >> 15) & 1) ? "streaming" : "return data buffer", "\n";
$msc0 = $msc0 >> 16;
print " - RT1: rom type: ", $msc0 & 0x7, "\n";
print " - RBW1: bus width: ", (($msc0 >> 3) & 1) ? "16" : "32", " bits\n";
print " - RDF1: rom delay first access: ", ($msc0 >> 4) & 0xf, "\n";
print " - RDN1: rom delay next access: ", ($msc0 >> 8) & 0xf, "\n";
print " - RRR1: rom/sram recovery time: ", ($msc0 >> 12) & 7, "\n";
print " - RBUFF1: return data: ", (($msc0 >> 15) & 1) ? "streaming" : "return data buffer", "\n";
}
sub ShowMSC1($)
{
my $msc1 = shift;
ShowReg('MSC1', $msc1, '6-44');
print " - RT2: rom type: ", $msc1 & 0x7, "\n";
print " - RBW2: bus width: ", (($msc1 >> 3) & 1) ? "16" : "32", " bits\n";
print " - RDF2: rom delay first access: ", ($msc1 >> 4) & 0xf, "\n";
print " - RDN2: rom delay next access: ", ($msc1 >> 8) & 0xf, "\n";
print " - RRR2: rom/sram recovery time: ", ($msc1 >> 12) & 7, "\n";
print " - RBUFF2: return data: ", (($msc1 >> 15) & 1) ? "streaming" : "return data buffer", "\n";
$msc1 = $msc1 >> 16;
print " - RT3: rom type: ", $msc1 & 0x7, "\n";
print " - RBW3: bus width: ", (($msc1 >> 3) & 1) ? "16" : "32", " bits\n";
print " - RDF3: rom delay first access: ", ($msc1 >> 4) & 0xf, "\n";
print " - RDN3: rom delay next access: ", ($msc1 >> 8) & 0xf, "\n";
print " - RRR3: rom/sram recovery time: ", ($msc1 >> 12) & 7, "\n";
print " - RBUFF3: return data: ", (($msc1 >> 15) & 1) ? "streaming" : "return data buffer", "\n";
}
sub ShowMSC2($)
{
my $msc2 = shift;
ShowReg('MSC2', $msc2, '6-44');
print " - RT0: rom type: ", $msc2 & 0x7, "\n";
print " - RBW4: bus width: ", (($msc2 >> 3) & 1) ? "16" : "32", " bits\n";
print " - RDF4: rom delay first access: ", ($msc2 >> 4) & 0xf, "\n";
print " - RDN4: rom delay next access: ", ($msc2 >> 8) & 0xf, "\n";
print " - RRR4: rom/sram recovery time: ", ($msc2 >> 12) & 7, "\n";
print " - RBUFF4: return data: ", (($msc2 >> 15) & 1) ? "streaming" : "return data buffer", "\n";
$msc2 = $msc2 >> 16;
print " - RT5: rom type: ", $msc2 & 0x7, "\n";
print " - RBW5: bus width: ", (($msc2 >> 3) & 1) ? "16" : "32", " bits\n";
print " - RDF5: rom delay first access: ", ($msc2 >> 4) & 0xf, "\n";
print " - RDN5: rom delay next access: ", ($msc2 >> 8) & 0xf, "\n";
print " - RRR5: rom/sram recovery time: ", ($msc2 >> 12) & 7, "\n";
print " - RBUFF5: return data: ", (($msc2 >> 15) & 1) ? "streaming" : "return data buffer", "\n";
}
sub ShowMCMEM0($)
{
my $mcmem0 = shift;
ShowReg('MCMEM0', $mcmem0, '6-57');
print " - SEXT: time before command assertion: ", $mcmem0 & 0x7f, "\n";
print " - ASST: command assertion time: ", ($mcmem0 >> 7) & 0x1f, "\n";
print " - HOLD: hold address time: ", ($mcmem0 >> 14) & 0x3f, "\n";
}
sub ShowMCMEM1($)
{
my $mcmem1 = shift;
ShowReg('MCMEM1', $mcmem1, '6-57');
print " - SEXT: time before command assertion: ", $mcmem1 & 0x7f, "\n";
print " - ASST: command assertion time: ", ($mcmem1 >> 7) & 0x1f, "\n";
print " - HOLD: hold address time: ", ($mcmem1 >> 14) & 0x3f, "\n";
}
sub ShowMDREFR($)
{
my $mdrefr = shift;
ShowReg('MDREFR', $mdrefr, '6-15');
print " - DRI: refresh interval, all partitions: ", $mdrefr & 0xfff, "\n";
print " - E0PIN: Clock Enable Pin 0: ", ($mdrefr >> 12) & 1, "\n";
print " - K0RUN: Clock Run Pin 0: ", ($mdrefr >> 13) & 1, "\n";
print " - K0DB2: Clock Pin 0 Divide/2: ", ($mdrefr >> 14) & 1, "\n";
print " - E1PIN: Clock Enable Pin 1: ", ($mdrefr >> 15) & 1, "\n";
print " - K1RUN: Clock Run Pin 1: ", ($mdrefr >> 16) & 1, "\n";
print " - K1DB2: Clock Pin 1 Divide/2: ", ($mdrefr >> 17) & 1, "\n";
print " - K2RUN: Clock Run Pin 2: ", ($mdrefr >> 18) & 1, "\n";
print " - K2DB2: Clock Pin 2 Divide/2: ", ($mdrefr >> 19) & 1, "\n";
print " - APD: Auto Power Down enable: ", ($mdrefr >> 20) & 1, "\n";
print " - SLFRSH: Self-Refresh: ", ($mdrefr >> 22) & 1, "\n";
print " - K0FREE: Free Running Control for SDCLK0: ", ($mdrefr >> 23) & 1, "\n";
print " - K1FREE: Free Running Control for SDCLK1: ", ($mdrefr >> 24) & 1, "\n";
print " - K2FREE: Free Running Control for SDCLK2: ", ($mdrefr >> 25) & 1, "\n";
}
sub ShowMDREFR_2($$$)
{
my ($mdrefr,$head,$comment) = @_;
if ($head) {
ShowReg('MDREFR', $mdrefr, '6-15');
print " E0 K0 K0 E1 K1 K1 K2 K2 SLF K0 K1 K2\n";
print " DRI PIN RUN DB2 PIN RUN DB2 RUN DB2 APD RSH FRE FRE FRE\n";
}
printf "0xx: M %-3d %-3d %-3d %-3d %-3d %-3d %-3d %-3d %-3d %-3d %-3d %-3d %-3d %s\n",
$mdrefr,
$mdrefr & 0xfff,
($mdrefr >> 12) & 1,
($mdrefr >> 13) & 1,
($mdrefr >> 14) & 1,
($mdrefr >> 15) & 1,
($mdrefr >> 16) & 1,
($mdrefr >> 17) & 1,
($mdrefr >> 18) & 1,
($mdrefr >> 19) & 1,
($mdrefr >> 20) & 1,
($mdrefr >> 22) & 1,
($mdrefr >> 23) & 1,
($mdrefr >> 24) & 1,
($mdrefr >> 25) & 1,
$comment;
=for me
print " - K0RUN: Clock Run Pin 0: ", ($mdrefr >> 13) & 1, "\n";
print " - K0DB2: Clock Pin 0 Divide/2: ", ($mdrefr >> 14) & 1, "\n";
print " - E1PIN: Clock Enable Pin 1: ", ($mdrefr >> 15) & 1, "\n";
print " - K1RUN: Clock Run Pin 1: ", ($mdrefr >> 16) & 1, "\n";
print " - K1DB2: Clock Pin 1 Divide/2: ", ($mdrefr >> 17) & 1, "\n";
print " - K2RUN: Clock Run Pin 2: ", ($mdrefr >> 18) & 1, "\n";
print " - K2DB2: Clock Pin 2 Divide/2: ", ($mdrefr >> 19) & 1, "\n";
print " - APD: Auto Power Down enable: ", ($mdrefr >> 20) & 1, "\n";
print " - SLFRSH: Self-Refresh: ", ($mdrefr >> 22) & 1, "\n";
print " - K0FREE: Free Running Control for SDCLK0: ", ($mdrefr >> 23) & 1, "\n";
print " - K1FREE: Free Running Control for SDCLK1: ", ($mdrefr >> 24) & 1, "\n";
print " - K2FREE: Free Running Control for SDCLK2: ", ($mdrefr >> 25) & 1, "\n";
=cut
}
sub ShowMDCNFG($)
{
my $mdcnfg = shift;
ShowReg('MDCNFG', $mdcnfg, '6-10');
print " - DE0: SDRAM enable for partition 0: ", $mdcnfg & 1, "\n";
print " - DE1: SDRAM enable for partition 1: ", ($mdcnfg >> 1) & 1, "\n";
print " - DWID0: SDRAM data bus width for partition 0/1: ", (($mdcnfg >> 2) & 1) ? 16:32, "\n";
print " - DCAC0: Column address bits for partition 0/1: ", (($mdcnfg >> 3) & 3) + 8, "\n";
print " - DRAC0: Row address bits for partition 0/1: ", (($mdcnfg >> 5) & 3) + 11, "\n";
print " - DNB0: number of banks in partition 0/1: ", (($mdcnfg >> 7) & 3) ? 4:2, "\n";
print " - DTC0: timing category in partition 0/1: ", (($mdcnfg >> 8) & 3), "\n";
print " - DADDR0: use alternate addressing in partition 0/1: ", (($mdcnfg >> 10) & 1), "\n";
print " - DLATCH0: return data in partition 0/1: ", (($mdcnfg >> 11) & 1), "\n";
print " - DSA1110_0: addressing mux mode for partition 0/1: ", (($mdcnfg >> 12) & 1), "\n";
print " - DE2: SDRAM enable for partition 2: ", ($mdcnfg >> 16) & 1, "\n";
print " - DE3: SDRAM enable for partition 3: ", ($mdcnfg >> 17) & 1, "\n";
print " - DWID2: SDRAM data bus width for partition 2/3: ", (($mdcnfg >> 18) & 1) ? 16:32, "\n";
print " - DCAC2: Column address bits for partition 2/3: ", (($mdcnfg >> 19) & 3) + 8, "\n";
print " - DRAC2: Row address bits for partition 2/3: ", (($mdcnfg >> 21) & 3) + 11, "\n";
print " - DNB2: number of banks in partition 2/3: ", (($mdcnfg >> 23) & 3) ? 4:2, "\n";
print " - DTC2: timing category in partition 2/3: ", (($mdcnfg >> 24) & 3), "\n";
print " - DADDR2: use alternate addressing in partition 2/3: ", (($mdcnfg >> 26) & 1), "\n";
print " - DLATCH2: return data in partition 2/3: ", (($mdcnfg >> 27) & 1), "\n";
print " - DSA1110_2: addressing mux mode for partition 2/3: ", (($mdcnfg >> 28) & 1), "\n";
}
sub ShowMDMRS($)
{
my $mdmrs = shift;
ShowReg('MDMRS', $mdmrs, '6-13');
print " - MDBL0: burst length partition 0/1: ", $mdmrs & 7, "\n";
print " - MDADD0: burst type partition 0/1: ", ($mdmrs >> 3) & 1, "\n";
print " - MDCL0: CAS latency parition 0/1: ", ($mdmrs >> 4) & 7, "\n";
print " - MDMRS0: MRS value to be written to SDRAM for partition 0/1: ", ($mdmrs >> 7) & 0xff, "\n";
print " - MDBL2: burst length partition 2/3: ", ($mdmrs >>16) & 7, "\n";
print " - MDADD2: burst type partition 2/3: ", ($mdmrs >> 19) & 1, "\n";
print " - MDCL2: CAS latency parition 2/3: ", ($mdmrs >> 20) & 7, "\n";
print " - MDMRS2: MRS value to be written to SDRAM for partition 2/3: ", ($mdmrs >> 23) & 0xff, "\n";
}
=for me
# Values from dcpxa250.cfg
ShowMSC0( 0x23F223F2);
ShowMSC1( 0x3FF1A441);
ShowMSC2( 0x7FF17FF1);
#ShowMECR( 0x00000000); # 6-60
ShowMCMEM0( 0x00010504);
ShowMCMEM1( 0x00010504);
#ShowMCATT0( 0x00010504);
#ShowMCATT1( 0x00010504);
#ShowMCIO0( 0x00004715);
#ShowMCIO1( 0x00004715);
ShowMDREFR( 0x000BC018);
ShowMDCNFG( 0x00001AC9);
ShowMDMRS( 0x00000000);
# Values once Linux is running
ShowMSC0( 0x229c2fd0);
ShowMSC1( 0x7ff42981);
ShowMSC2( 0x29847ff4);
#ShowMECR( 0x00000003);
ShowMCMEM0( 0x00014699);
ShowMCMEM1( 0x00014699);
#ShowMCATT0( 0x00014699);
#ShowMCATT1( 0x00014699);
#ShowMCIO0( 0x00014699);
#ShowMCIO1( 0x00014699);
ShowMDREFR( 0x0085c017);
ShowMDCNFG( 0x0a000ac9);
ShowMDMRS( 0x00320032);
# Values to be used in the bootloader
ShowMSC0( 0x2fd02fd0);
ShowMSC1( 0x7ff42981);
ShowMSC2( 0x7ff47ff4);
#ShowMECR( 0x00000000);
ShowMCMEM0( 0x00014699);
ShowMCMEM1( 0x00014699);
#ShowMCATT0( 0x00014699);
#ShowMCATT1( 0x00014699);
#ShowMCIO0( 0x00014699);
#ShowMCIO1( 0x00014699);
ShowMDREFR( 0x000183ff);
ShowMDCNFG( 0x00001AC9);
ShowMDMRS( 0x00320032);
=cut
ShowMSC(0x229C2FD0,0x538C2981,0x29847FD1); # armboot
#ShowMSC(0x229C2FD0,0x538C2981,0x2CC47FD4); # Accelent
#ShowMECR( 0x00000003);
#ShowMCMEM0( 0x00014699);
#ShowMCMEM1( 0x00014699);
#ShowMCATT0( 0x00014699);
#ShowMCATT1( 0x00014699);
#ShowMCIO0( 0x00014699);
#ShowMCIO1( 0x00014699);
#FLYCNFG
ShowMDREFR_2(0x00400017,1,'2d');
ShowMDREFR_2(0x00410017,0,'4a');
ShowMDREFR_2(0x00010017,0,'4b');
ShowMDREFR_2(0x00018017,0,'4c');
#ShowMDCNFG( 0x00000AC8); # do "| 2" to enable partition 1, too
# wait 200 usec
# trigger IO
#ShowMDCNFG( 0x00000ACB); # do "| 2" to enable partition 1, too
#ShowMDMRS( 0x00320032);
ShowMDREFR_2(0x00018017 | (1<<20),0,'optional 5');
#ShowMDREFR_2(0x0085C017 ,0,'Accelent');